1The pinctrl driver enables Marvell Armada 8K SoCs to configure the multi-purpose
2pins (mpp) to a specific function.
3A Marvell SoC pin configuration node is a node of a group of pins which can
4be used for a specific device or function. Each node requires one or more
5mpp pins or group of pins and a mpp function common to all pins.
6
7Required properties for the pinctrl driver:
8- compatible:	"marvell,mvebu-pinctrl",
9		"marvell,ap806-pinctrl",
10		"marvell,armada-7k-pinctrl",
11		"marvell,armada-8k-cpm-pinctrl",
12		"marvell,armada-8k-cps-pinctrl"
13- bank-name:	A string defining the pinc controller bank name
14- reg: 		A pair of values defining the pin controller base address
15		and the address space
16- pin-count:	Numeric value defining the amount of multi purpose pins
17		included in this bank
18- max-func:	Numeric value defining the maximum function value for
19		pins in this bank
20- pin-func:	Array of pin function values for every pin in the bank.
21		When the function value for a specific pin equal 0xFF,
22		the pin configuration is skipped and a default function
23		value is used for this pin.
24
25The A8K is a hybrid SoC that contains several silicon dies interconnected in
26a single package. Each such die may have a separate pin controller.
27
28Example:
29/ {
30	ap806 {
31		config-space {
32			pinctl: pinctl@6F4000 {
33				compatible = "marvell,mvebu-pinctrl",
34					     "marvell,ap806-pinctrl";
35				bank-name ="apn-806";
36				reg = <0x6F4000 0x10>;
37				pin-count = <20>;
38				max-func = <3>;
39				/* MPP Bus:
40				 * SPI0 [0-3]
41				 * I2C0 [4-5]
42				 * UART0 [11,19]
43				 */
44					  /* 0 1 2 3 4 5 6 7 8 9 */
45				pin-func = < 3 3 3 3 3 3 0 0 0 0
46					     0 3 0 0 0 0 0 0 0 3>;
47			};
48		};
49	};
50
51	cp110-master {
52		config-space {
53			cpm_pinctl: pinctl@44000 {
54				compatible = "marvell,mvebu-pinctrl",
55					     "marvell,armada-7k-pinctrl",
56					     "marvell,armada-8k-cpm-pinctrl";
57				bank-name ="cp0-110";
58				reg = <0x440000 0x20>;
59				pin-count = <63>;
60				max-func = <0xf>;
61				/* MPP Bus:
62				 * [0-31] = 0xff: Keep default CP0_shared_pins:
63				 * [11] CLKOUT_MPP_11 (out)
64				 * [23] LINK_RD_IN_CP2CP (in)
65				 * [25] CLKOUT_MPP_25 (out)
66				 * [29] AVS_FB_IN_CP2CP (in)
67				 * [32,34] SMI
68				 * [31]    GPIO: push button/Wake
69				 * [35-36] GPIO
70				 * [37-38] I2C
71				 * [40-41] SATA[0/1]_PRESENT_ACTIVEn
72				 * [42-43] XSMI
73				 * [44-55] RGMII1
74				 * [56-62] SD
75				 */
76					/*   0    1    2    3    4    5    6    7    8    9 */
77				pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
78					     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
79					     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
80					     0xff 0    7    0    7    0    0    2    2    0
81					     0    0    8    8    1    1    1    1    1    1
82					     1    1    1    1    1    1    0xE  0xE  0xE  0xE
83					     0xE  0xE  0xE>;
84			};
85		};
86	};
87
88	cp110-slave {
89		config-space {
90			cps_pinctl: pinctl@44000 {
91				compatible = "marvell,mvebu-pinctrl",
92					     "marvell,armada-8k-cps-pinctrl";
93				bank-name ="cp1-110";
94				reg = <0x440000 0x20>;
95				pin-count = <63>;
96				max-func = <0xf>;
97				/* MPP Bus:
98				 * [0-11]  RGMII0
99				 * [27,31] GE_MDIO/MDC
100				 * [32-62] = 0xff: Keep default CP1_shared_pins:
101				 */
102					/*   0    1    2    3    4    5    6    7    8    9 */
103				pin-func = < 0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3
104					     0x3  0x3  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
105					     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8  0xff 0xff
106					     0xff 0x8  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
107					     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
108					     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
109					     0xff 0xff 0xff>;
110			};
111		};
112	};
113}
114