1656e6cc8SKonstantin PorotchkinThe pinctrl driver enables Marvell Armada 8K SoCs to configure the multi-purpose 2656e6cc8SKonstantin Porotchkinpins (mpp) to a specific function. 3656e6cc8SKonstantin PorotchkinA Marvell SoC pin configuration node is a node of a group of pins which can 4656e6cc8SKonstantin Porotchkinbe used for a specific device or function. Each node requires one or more 5656e6cc8SKonstantin Porotchkinmpp pins or group of pins and a mpp function common to all pins. 6656e6cc8SKonstantin Porotchkin 7656e6cc8SKonstantin PorotchkinRequired properties for the pinctrl driver: 8656e6cc8SKonstantin Porotchkin- compatible: "marvell,mvebu-pinctrl", 9656e6cc8SKonstantin Porotchkin "marvell,armada-ap806-pinctrl", 10656e6cc8SKonstantin Porotchkin "marvell,a70x0-pinctrl", 11656e6cc8SKonstantin Porotchkin "marvell,a80x0-cp0-pinctrl", 12656e6cc8SKonstantin Porotchkin "marvell,a80x0-cp1-pinctrl" 13656e6cc8SKonstantin Porotchkin- bank-name: A string defining the pinc controller bank name 14656e6cc8SKonstantin Porotchkin- reg: A pair of values defining the pin controller base address 15656e6cc8SKonstantin Porotchkin and the address space 16656e6cc8SKonstantin Porotchkin- pin-count: Numeric value defining the amount of multi purpose pins 17656e6cc8SKonstantin Porotchkin included in this bank 18656e6cc8SKonstantin Porotchkin- max-func: Numeric value defining the maximum function value for 19656e6cc8SKonstantin Porotchkin pins in this bank 20656e6cc8SKonstantin Porotchkin- pin-func: Array of pin function values for every pin in the bank. 21656e6cc8SKonstantin Porotchkin When the function value for a specific pin equal 0xFF, 22656e6cc8SKonstantin Porotchkin the pin configuration is skipped and a default function 23656e6cc8SKonstantin Porotchkin value is used for this pin. 24656e6cc8SKonstantin Porotchkin 25656e6cc8SKonstantin PorotchkinThe A8K is a hybrid SoC that contains several silicon dies interconnected in 26656e6cc8SKonstantin Porotchkina single package. Each such die may have a separate pin controller. 27656e6cc8SKonstantin Porotchkin 28656e6cc8SKonstantin PorotchkinExample: 29656e6cc8SKonstantin Porotchkin/ { 30656e6cc8SKonstantin Porotchkin ap806 { 31656e6cc8SKonstantin Porotchkin config-space { 32656e6cc8SKonstantin Porotchkin pinctl: pinctl@6F4000 { 33656e6cc8SKonstantin Porotchkin compatible = "marvell,mvebu-pinctrl", 34656e6cc8SKonstantin Porotchkin "marvell,armada-ap806-pinctrl"; 35656e6cc8SKonstantin Porotchkin bank-name ="apn-806"; 36656e6cc8SKonstantin Porotchkin reg = <0x6F4000 0x10>; 37656e6cc8SKonstantin Porotchkin pin-count = <20>; 38656e6cc8SKonstantin Porotchkin max-func = <3>; 39656e6cc8SKonstantin Porotchkin /* MPP Bus: 40*f99386c5SKonstantin Porotchkin * SPI0 [0-3] 41*f99386c5SKonstantin Porotchkin * I2C0 [4-5] 42*f99386c5SKonstantin Porotchkin * UART0 [11,19] 43656e6cc8SKonstantin Porotchkin */ 44656e6cc8SKonstantin Porotchkin /* 0 1 2 3 4 5 6 7 8 9 */ 45656e6cc8SKonstantin Porotchkin pin-func = < 3 3 3 3 3 3 0 0 0 0 46656e6cc8SKonstantin Porotchkin 0 3 0 0 0 0 0 0 0 3>; 47656e6cc8SKonstantin Porotchkin }; 48656e6cc8SKonstantin Porotchkin }; 49656e6cc8SKonstantin Porotchkin }; 50656e6cc8SKonstantin Porotchkin 51656e6cc8SKonstantin Porotchkin cp110-master { 52656e6cc8SKonstantin Porotchkin config-space { 53656e6cc8SKonstantin Porotchkin cpm_pinctl: pinctl@44000 { 54656e6cc8SKonstantin Porotchkin compatible = "marvell,mvebu-pinctrl", 55656e6cc8SKonstantin Porotchkin "marvell,a70x0-pinctrl", 56656e6cc8SKonstantin Porotchkin "marvell,a80x0-cp0-pinctrl"; 57656e6cc8SKonstantin Porotchkin bank-name ="cp0-110"; 58656e6cc8SKonstantin Porotchkin reg = <0x440000 0x20>; 59656e6cc8SKonstantin Porotchkin pin-count = <63>; 60656e6cc8SKonstantin Porotchkin max-func = <0xf>; 61656e6cc8SKonstantin Porotchkin /* MPP Bus: 62*f99386c5SKonstantin Porotchkin * [0-31] = 0xff: Keep default CP0_shared_pins: 63*f99386c5SKonstantin Porotchkin * [11] CLKOUT_MPP_11 (out) 64*f99386c5SKonstantin Porotchkin * [23] LINK_RD_IN_CP2CP (in) 65*f99386c5SKonstantin Porotchkin * [25] CLKOUT_MPP_25 (out) 66*f99386c5SKonstantin Porotchkin * [29] AVS_FB_IN_CP2CP (in) 67*f99386c5SKonstantin Porotchkin * [32,34] SMI 68*f99386c5SKonstantin Porotchkin * [31] GPIO: push button/Wake 69*f99386c5SKonstantin Porotchkin * [35-36] GPIO 70*f99386c5SKonstantin Porotchkin * [37-38] I2C 71*f99386c5SKonstantin Porotchkin * [40-41] SATA[0/1]_PRESENT_ACTIVEn 72*f99386c5SKonstantin Porotchkin * [42-43] XSMI 73*f99386c5SKonstantin Porotchkin * [44-55] RGMII1 74*f99386c5SKonstantin Porotchkin * [56-62] SD 75656e6cc8SKonstantin Porotchkin */ 76656e6cc8SKonstantin Porotchkin /* 0 1 2 3 4 5 6 7 8 9 */ 77656e6cc8SKonstantin Porotchkin pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 78656e6cc8SKonstantin Porotchkin 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 79656e6cc8SKonstantin Porotchkin 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 80656e6cc8SKonstantin Porotchkin 0xff 0 7 0 7 0 0 2 2 0 81656e6cc8SKonstantin Porotchkin 0 0 8 8 1 1 1 1 1 1 82656e6cc8SKonstantin Porotchkin 1 1 1 1 1 1 0xE 0xE 0xE 0xE 83656e6cc8SKonstantin Porotchkin 0xE 0xE 0xE>; 84656e6cc8SKonstantin Porotchkin }; 85656e6cc8SKonstantin Porotchkin }; 86656e6cc8SKonstantin Porotchkin }; 87656e6cc8SKonstantin Porotchkin 88656e6cc8SKonstantin Porotchkin cp110-slave { 89656e6cc8SKonstantin Porotchkin config-space { 90656e6cc8SKonstantin Porotchkin cps_pinctl: pinctl@44000 { 91656e6cc8SKonstantin Porotchkin compatible = "marvell,mvebu-pinctrl", 92656e6cc8SKonstantin Porotchkin "marvell,a80x0-cp1-pinctrl"; 93656e6cc8SKonstantin Porotchkin bank-name ="cp1-110"; 94656e6cc8SKonstantin Porotchkin reg = <0x440000 0x20>; 95656e6cc8SKonstantin Porotchkin pin-count = <63>; 96656e6cc8SKonstantin Porotchkin max-func = <0xf>; 97656e6cc8SKonstantin Porotchkin /* MPP Bus: 98*f99386c5SKonstantin Porotchkin * [0-11] RGMII0 99*f99386c5SKonstantin Porotchkin * [27,31] GE_MDIO/MDC 100*f99386c5SKonstantin Porotchkin * [32-62] = 0xff: Keep default CP1_shared_pins: 101656e6cc8SKonstantin Porotchkin */ 102656e6cc8SKonstantin Porotchkin /* 0 1 2 3 4 5 6 7 8 9 */ 103656e6cc8SKonstantin Porotchkin pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 104656e6cc8SKonstantin Porotchkin 0x3 0x3 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 105656e6cc8SKonstantin Porotchkin 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0xff 0xff 106656e6cc8SKonstantin Porotchkin 0xff 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 107656e6cc8SKonstantin Porotchkin 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 108656e6cc8SKonstantin Porotchkin 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 109656e6cc8SKonstantin Porotchkin 0xff 0xff 0xff>; 110656e6cc8SKonstantin Porotchkin }; 111656e6cc8SKonstantin Porotchkin }; 112656e6cc8SKonstantin Porotchkin }; 113656e6cc8SKonstantin Porotchkin} 114