1Intel LPC Device Binding
2========================
3
4The device tree node which describes the operation of the Intel Low Pin
5Count device is as follows:
6
7Required properties :
8- compatible = "intel,lpc"
9- intel,alt-gp-smi-enable : Enable SMI sources. This cell is written to the
10    ALT_GP_SMI_EN register
11- intel,gen-dec : Specifies the values for the gen-dec registers. Up to four
12   cell pairs can be provided - the first of each pair is the base address and
13   the second is the size. These are written into the GENx_DEC registers of
14   the LPC device
15- intel,gpi-routing : Specifies the GPI routing. There are 16 cells, valid
16   values are:
17     0 No effect (default)
18     1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
19     2 SCI (if corresponding GPIO_EN bit is also set)
20- intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H,
21   one cell for each.
22     0x00 - 0000 = Reserved
23     0x01 - 0001 = Reserved
24     0x02 - 0010 = Reserved
25     0x03 - 0011 = IRQ3
26     0x04 - 0100 = IRQ4
27     0x05 - 0101 = IRQ5
28     0x06 - 0110 = IRQ6
29     0x07 - 0111 = IRQ7
30     0x08 - 1000 = Reserved
31     0x09 - 1001 = IRQ9
32     0x0A - 1010 = IRQ10
33     0x0B - 1011 = IRQ11
34     0x0C - 1100 = IRQ12
35     0x0D - 1101 = Reserved
36     0x0E - 1110 = IRQ14
37     0x0F - 1111 = IRQ15
38     PIRQ[n]_ROUT[7] - PIRQ Routing Control
39     0x80 - The PIRQ is not routed.
40
41
42Example
43-------
44
45lpc {
46	compatible = "intel,lpc";
47	#address-cells = <1>;
48	#size-cells = <1>;
49	intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
50
51	intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
52				0x80 0x80 0x80 0x80>;
53	/*
54		* GPI routing
55		* 0 No effect (default)
56		* 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is
57		*	also set)
58		* 2 SCI (if corresponding GPIO_EN bit is also set)
59		*/
60	intel,gpi-routing = <0 0 0 0 0 0 0 2
61				1 0 0 0 0 0 0 0>;
62	/* Enable EC SMI source */
63	intel,alt-gp-smi-enable = <0x0100>;
64};
65