1Intel Interrupt Router Device Binding
2=====================================
3
4The device tree node which describes the operation of the Intel Interrupt Router
5device is as follows:
6
7Required properties :
8- reg : Specifies the interrupt router's PCI configuration space address as
9    defined by the Open Firmware spec.
10- compatible = "intel,irq-router"
11- intel,pirq-config : Specifies the IRQ routing register programming mechanism.
12    Valid values are:
13      "pci": IRQ routing is controlled by PCI configuration registers
14      "ibase": IRQ routing is in the memory-mapped IBASE register block
15- intel,ibase-offset : IBASE register offset in the interrupt router's PCI
16    configuration space, required only if intel,pirq-config = "ibase".
17- intel,pirq-link : Specifies the PIRQ link information with two cells. The
18    first cell is the register offset that controls the first PIRQ link routing.
19    The second cell is the total number of PIRQ links the router supports.
20- intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the
21    8259 PIC. Bit N is 1 means IRQ N is available to be routed.
22- intel,pirq-routing : Specifies all PCI devices' IRQ routing information,
23   encoded as 3 cells a group for a device. The first cell is the device's PCI
24   bus number, device number and function number encoding with PCI_BDF() macro.
25   The second cell is the PCI interrupt pin used by this device. The last cell
26   is which PIRQ line the PCI interrupt pin is routed to.
27
28
29Example
30-------
31
32#include <dt-bindings/interrupt-router/intel-irq.h>
33
34	irq-router@1f,0 {
35		reg = <0x0000f800 0 0 0 0>;
36		compatible = "intel,irq-router";
37		intel,pirq-config = "pci";
38		intel,pirq-link = <0x60 8>;
39		intel,pirq-mask = <0xdef8>;
40		intel,pirq-routing = <
41			PCI_BDF(0, 2, 0) INTA PIRQA
42			PCI_BDF(0, 3, 0) INTA PIRQB
43			PCI_BDF(0, 8, 0) INTA PIRQC
44			PCI_BDF(0, 8, 1) INTB PIRQD
45			PCI_BDF(1, 6, 0) INTA PIRQE
46			PCI_BDF(1, 6, 1) INTB PIRQF
47			PCI_BDF(1, 6, 2) INTC PIRQG
48			PCI_BDF(1, 6, 3) INTD PIRQH
49		>;
50	};
51