1Intel Interrupt Router Device Binding 2===================================== 3 4The device tree node which describes the operation of the Intel Interrupt Router 5device is as follows: 6 7Required properties : 8- reg : Specifies the interrupt router's PCI configuration space address as 9 defined by the Open Firmware spec. 10- compatible = "intel,irq-router" 11- intel,pirq-config : Specifies the IRQ routing register programming mechanism. 12 Valid values are: 13 "pci": IRQ routing is controlled by PCI configuration registers 14 "ibase": IRQ routing is in the memory-mapped IBASE register block 15- intel,ibase-offset : IBASE register offset in the interrupt router's PCI 16 configuration space, required only if intel,pirq-config = "ibase". 17- intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must 18 be specified. The 8-bit ACTL register is seen on ICH series chipset, like 19 ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register. 20- intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either 21 in the interrupt router's PCI configuration space, or IBASE. 22- intel,pirq-link : Specifies the PIRQ link information with two cells. The 23 first cell is the register offset that controls the first PIRQ link routing. 24 The second cell is the total number of PIRQ links the router supports. 25- intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the 26 8259 PIC. Bit N is 1 means IRQ N is available to be routed. 27- intel,pirq-routing : Specifies all PCI devices' IRQ routing information, 28 encoded as 3 cells a group for a device. The first cell is the device's PCI 29 bus number, device number and function number encoding with PCI_BDF() macro. 30 The second cell is the PCI interrupt pin used by this device. The last cell 31 is which PIRQ line the PCI interrupt pin is routed to. 32 33 34Example 35------- 36 37#include <dt-bindings/interrupt-router/intel-irq.h> 38 39 irq-router@1f,0 { 40 reg = <0x0000f800 0 0 0 0>; 41 compatible = "intel,irq-router"; 42 intel,pirq-config = "pci"; 43 intel,pirq-link = <0x60 8>; 44 intel,pirq-mask = <0xdef8>; 45 intel,pirq-routing = < 46 PCI_BDF(0, 2, 0) INTA PIRQA 47 PCI_BDF(0, 3, 0) INTA PIRQB 48 PCI_BDF(0, 8, 0) INTA PIRQC 49 PCI_BDF(0, 8, 1) INTB PIRQD 50 PCI_BDF(1, 6, 0) INTA PIRQE 51 PCI_BDF(1, 6, 1) INTB PIRQF 52 PCI_BDF(1, 6, 2) INTC PIRQG 53 PCI_BDF(1, 6, 3) INTD PIRQH 54 >; 55 }; 56