1*3a29afcbSPatrick DelaunayST, stm32 flexible memory controller Drive 2*3a29afcbSPatrick DelaunayRequired properties: 3*3a29afcbSPatrick Delaunay- compatible : "st,stm32-fmc" 4*3a29afcbSPatrick Delaunay- reg : fmc controller base address 5*3a29afcbSPatrick Delaunay- clocks : fmc controller clock 6*3a29afcbSPatrick Delaunayu-boot,dm-pre-reloc: flag to initialize memory before relocation. 7*3a29afcbSPatrick Delaunay 8*3a29afcbSPatrick Delaunayon-board sdram memory attributes: 9*3a29afcbSPatrick Delaunay- st,sdram-control : parameters for sdram configuration, in this order: 10*3a29afcbSPatrick Delaunay number of columns 11*3a29afcbSPatrick Delaunay number of rows 12*3a29afcbSPatrick Delaunay memory width 13*3a29afcbSPatrick Delaunay number of intenal banks in memory 14*3a29afcbSPatrick Delaunay cas latency 15*3a29afcbSPatrick Delaunay read burst enable or disable 16*3a29afcbSPatrick Delaunay read pipe delay 17*3a29afcbSPatrick Delaunay 18*3a29afcbSPatrick Delaunay- st,sdram-timing: timings for sdram, in this order: 19*3a29afcbSPatrick Delaunay tmrd 20*3a29afcbSPatrick Delaunay txsr 21*3a29afcbSPatrick Delaunay tras 22*3a29afcbSPatrick Delaunay trc 23*3a29afcbSPatrick Delaunay trp 24*3a29afcbSPatrick Delaunay trcd 25*3a29afcbSPatrick Delaunay 26*3a29afcbSPatrick DelaunayThere is device tree include file at : 27*3a29afcbSPatrick Delaunayinclude/dt-bindings/memory/stm32-sdram.h to define sdram control and timing 28*3a29afcbSPatrick Delaunayparameters as MACROS. 29*3a29afcbSPatrick Delaunay 30*3a29afcbSPatrick DelaunayExample: 31*3a29afcbSPatrick Delaunay fmc: fmc@A0000000 { 32*3a29afcbSPatrick Delaunay compatible = "st,stm32-fmc"; 33*3a29afcbSPatrick Delaunay reg = <0xA0000000 0x1000>; 34*3a29afcbSPatrick Delaunay clocks = <&rcc 0 64>; 35*3a29afcbSPatrick Delaunay u-boot,dm-pre-reloc; 36*3a29afcbSPatrick Delaunay }; 37*3a29afcbSPatrick Delaunay 38*3a29afcbSPatrick Delaunay &fmc { 39*3a29afcbSPatrick Delaunay pinctrl-0 = <&fmc_pins>; 40*3a29afcbSPatrick Delaunay pinctrl-names = "default"; 41*3a29afcbSPatrick Delaunay status = "okay"; 42*3a29afcbSPatrick Delaunay 43*3a29afcbSPatrick Delaunay /* sdram memory configuration from sdram datasheet */ 44*3a29afcbSPatrick Delaunay bank1: bank@0 { 45*3a29afcbSPatrick Delaunay st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 46*3a29afcbSPatrick Delaunay CAS_3 RD_BURST_EN RD_PIPE_DL_0>; 47*3a29afcbSPatrick Delaunay st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 48*3a29afcbSPatrick Delaunay TRCD_18>; 49*3a29afcbSPatrick Delaunay }; 50*3a29afcbSPatrick Delaunay 51*3a29afcbSPatrick Delaunay /* sdram memory configuration from sdram datasheet */ 52*3a29afcbSPatrick Delaunay bank2: bank@1 { 53*3a29afcbSPatrick Delaunay st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 54*3a29afcbSPatrick Delaunay CAS_3 RD_BURST_EN RD_PIPE_DL_0>; 55*3a29afcbSPatrick Delaunay st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 56*3a29afcbSPatrick Delaunay TRCD_18>; 57*3a29afcbSPatrick Delaunay }; 58*3a29afcbSPatrick Delaunay } 59