1Texas Instruments' K3 AM654 DDRSS
2=================================
3
4K3 based AM654 devices has DDR memory subsystem that comprises
5Synopys DDR controller, Synopsis DDR phy and wrapper logic to
6integrate these blocks into the device. This DDR subsystem
7provides an interface to external SDRAM devices. This DDRSS driver
8adds support for the initialization of the external SDRAM devices by
9configuring the DDRSS registers and using the buitin PHY
10initialization routines.
11
12DDRSS device node:
13==================
14Required properties:
15--------------------
16- compatible:		Shall be: "ti,am654-ddrss"
17- reg-names 		ss - Map the sub system wrapper logic region
18			ctl - Map the controller region
19			phy - Map the PHY region
20- reg:			Contains the register map per reg-names.
21- power-domains:	Should contain a phandle to a PM domain provider node
22			and an args specifier containing the DDRSS device id
23			value. This property is as per the binding,
24			doc/device-tree-bindings/power/ti,sci-pm-domain.txt
25- clocks:		Must contain an entry for enabling DDR clock. Should
26			be defined as per the appropriate clock bindings consumer
27			usage in doc/device-tree-bindings/clock/ti,sci-clk.txt
28
29
30Optional Properties:
31--------------------
32- clock-frequency:	Frequency at which DDR pll should be locked.
33			If not provided, default frequency will be used.
34
35Example (AM65x):
36================
37		memory-controller: memory-controller@298e000 {
38			compatible = "ti,am654-ddrss";
39			reg = <0x0298e000 0x200>,
40				<0x02980000 0x4000>,
41				<0x02988000 0x2000>;
42			reg-names = "ss", "ctl", "phy";
43			clocks = <&k3_clks 20 0>;
44			power-domains = <&k3_pds 20>;
45			u-boot,dm-spl;
46		};
47