1*2a48c15dSLars PovlsenMicrosemi Corporation (MSCC) Serial GPIO driver 2*2a48c15dSLars Povlsen 3*2a48c15dSLars PovlsenThe MSCC serial GPIO extends the number or GPIO's on the system by 4*2a48c15dSLars Povlsenmeans of 4 dedicated pins: one input, one output, one clock and one 5*2a48c15dSLars Povlsenstrobe pin. By attaching a number of (external) shift registers, the 6*2a48c15dSLars Povlseneffective GPIO count can be extended by up to 128 GPIO's per 7*2a48c15dSLars Povlsencontroller. 8*2a48c15dSLars Povlsen 9*2a48c15dSLars PovlsenRequired properties: 10*2a48c15dSLars Povlsen- compatible : "mscc,luton-sgpio" or "mscc,ocelot-sgpio" 11*2a48c15dSLars Povlsen- clock: Reference clock used to generate clock divider setting. See 12*2a48c15dSLars Povlsen mscc,sgpio-frequency property. 13*2a48c15dSLars Povlsen- reg : Physical base address and length of the controller's registers. 14*2a48c15dSLars Povlsen- #gpio-cells : Should be two. The first cell is the pin number and the 15*2a48c15dSLars Povlsen second cell is used to specify optional parameters: 16*2a48c15dSLars Povlsen - bit 0 specifies polarity (0 for normal, 1 for inverted) 17*2a48c15dSLars Povlsen- gpio-controller : Marks the device node as a GPIO controller. 18*2a48c15dSLars Povlsen- gpio-ranges: Standard gpio range(s): phandle, gpio base, pinctrl base 19*2a48c15dSLars Povlsen and count. 20*2a48c15dSLars Povlsen 21*2a48c15dSLars PovlsenOptional properties: 22*2a48c15dSLars Povlsen- ngpios: See gpio.txt 23*2a48c15dSLars Povlsen- mscc,sgpio-frequency: The frequency at which the serial bitstream is 24*2a48c15dSLars Povlsen generated and sampled. Default: 12500000 (Hz). 25*2a48c15dSLars Povlsen- mscc,sgpio-ports: A bitmask (32 bits) of which ports are enabled in 26*2a48c15dSLars Povlsen the serialized gpio stream. One 'port' will transport from 1 to 4 27*2a48c15dSLars Povlsen gpio bits. Default: 0xFFFFFFFF. 28*2a48c15dSLars Povlsen 29*2a48c15dSLars PovlsenTypically the pinctrl-0 and pinctrl-names properties will also be 30*2a48c15dSLars Povlsenpresent to enable the use of the SIO CLK, LD, DI and DO for some 31*2a48c15dSLars Povlsenregular GPIO pins. 32*2a48c15dSLars Povlsen 33*2a48c15dSLars PovlsenExample: 34*2a48c15dSLars Povlsen 35*2a48c15dSLars Povlsensgpio: gpio@10700f8 { 36*2a48c15dSLars Povlsen compatible = "mscc,ocelot-sgpio"; 37*2a48c15dSLars Povlsen pinctrl-0 = <&sgpio_pins>; 38*2a48c15dSLars Povlsen pinctrl-names = "default"; 39*2a48c15dSLars Povlsen reg = <0x10700f8 0x100>; 40*2a48c15dSLars Povlsen gpio-controller; 41*2a48c15dSLars Povlsen #gpio-cells = <2>; 42*2a48c15dSLars Povlsen gpio-ranges = <&sgpio 0 0 64>; 43*2a48c15dSLars Povlsen mscc,sgpio-frequency = <12500>; 44*2a48c15dSLars Povlsen mscc,sgpio-ports = <0x000FFFFF>; 45*2a48c15dSLars Povlsen}; 46