xref: /openbmc/u-boot/doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt (revision eba6589f7e019d8ccb331a84a789b0c4d74f51f6)
1 Intel x86 PINCTRL/GPIO controller
2 
3 Pin-muxing on broadwell devices can be described with a node for the PINCTRL
4 master node and a set of child nodes for each required pin state on the SoC.
5 These pin states use phandles and are referred to but a configuration section
6 which lists all pins in the device.
7 
8 The PINCTRL master node requires the following properties:
9 - compatible : "intel,x86-broadwell-pinctrl"
10 
11 Pin state nodes must be sub-nodes of the pinctrl master node. The must have
12 a phandle. They can contain the following optional properties:
13 - mode-gpio	- forces the pin into GPIO mode
14 - output-value	- sets the default output value of the GPIO, 0 (low, default)
15 			or 1 (high)
16 - direction	- sets the direction of the gpio, either PIN_INPUT (default)
17 			or PIN_OUTPUT
18 - invert	- the input pin is inverted
19 - trigger	- sets the trigger type, either TRIGGER_EDGE (default) or
20 			TRIGGER_LEVEL
21 - sense-disable - the input state sense is disabled
22 - owner		0 sets the owner of the pin, either OWNER_ACPI (default) or
23 			ONWER_GPIO
24 - route		- sets whether the pin is routed, either PIRQ_APIC_MASK or
25 			PIRQ_APIC_ROUTE
26 - irq-enable	- the interrupt is enabled
27 - reset-rsmrst	- the pin will only be reset by RSMRST
28 - pirq-apic	- the pin will be routed to the IOxAPIC
29 
30 The first pin state will be the default, so pins without a configuration will
31 use that.
32 
33 The pin configuration node is also a sub-node of the pinctrl master node, but
34 does not have a phandle. It has a single property:
35 
36 - config	- configuration to use for each pin. Each entry has of 3 cells:
37 			- GPIO number (0..94)
38 			- phandle of configuration (above)
39 			- interrupt number (0..15)
40 
41 		  There should be one entry for each pin (i.e. 95 entries).
42 		  But missing pins will receive the default configuration.
43 
44 Example:
45 
46 pch_pinctrl {
47 	compatible = "intel,x86-broadwell-pinctrl";
48 
49 	/* Put this first: it is the default */
50 	gpio_unused: gpio-unused {
51 		mode-gpio;
52 		direction = <PIN_INPUT>;
53 		owner = <OWNER_GPIO>;
54 		sense-disable;
55 	};
56 
57 	gpio_acpi_sci: acpi-sci {
58 		mode-gpio;
59 		direction = <PIN_INPUT>;
60 		invert;
61 		route = <ROUTE_SCI>;
62 	};
63 
64 	gpio_acpi_smi: acpi-smi {
65 		mode-gpio;
66 		direction = <PIN_INPUT>;
67 		invert;
68 		route = <ROUTE_SMI>;
69 	};
70 
71 	gpio_input: gpio-input {
72 		mode-gpio;
73 		direction = <PIN_INPUT>;
74 		owner = <OWNER_GPIO>;
75 	};
76 
77 	gpio_input_invert: gpio-input-invert {
78 		mode-gpio;
79 		direction = <PIN_INPUT>;
80 		owner = <OWNER_GPIO>;
81 		invert;
82 	};
83 
84 	gpio_native: gpio-native {
85 	};
86 
87 	gpio_out_high: gpio-out-high {
88 		mode-gpio;
89 		direction = <PIN_OUTPUT>;
90 		output-value = <1>;
91 		owner = <OWNER_GPIO>;
92 		sense-disable;
93 	};
94 
95 	gpio_out_low: gpio-out-low {
96 		mode-gpio;
97 		direction = <PIN_OUTPUT>;
98 		output-value = <0>;
99 		owner = <OWNER_GPIO>;
100 		sense-disable;
101 	};
102 
103 	gpio_pirq: gpio-pirq {
104 		mode-gpio;
105 		direction = <PIN_INPUT>;
106 		owner = <OWNER_GPIO>;
107 		pirq-apic = <PIRQ_APIC_ROUTE>;
108 	};
109 
110 	soc_gpio@0 {
111 		config =
112 			<0 &gpio_unused 0>,	/* unused */
113 			<1 &gpio_unused 0>,	/* unused */
114 			<2 &gpio_unused 0>,	/* unused */
115 			<3 &gpio_unused 0>,	/* unused */
116 			<4 &gpio_native 0>,	/* native: i2c0_sda_gpio4 */
117 			<5 &gpio_native 0>,	/* native: i2c0_scl_gpio5 */
118 			<6 &gpio_native 0>,	/* native: i2c1_sda_gpio6 */
119 			<7 &gpio_native 0>,	/* native: i2c1_scl_gpio7 */
120 			<8 &gpio_acpi_sci 0>,	/* pch_lte_wake_l */
121 			<9 &gpio_input_invert 0>,/* trackpad_int_l (wake) */
122 			<10 &gpio_acpi_sci 0>,	/* pch_wlan_wake_l */
123 			<11 &gpio_unused 0>,	/* unused */
124 			<12 &gpio_unused 0>,	/* unused */
125 			<13 &gpio_pirq 3>,	/* trackpad_int_l (pirql) */
126 			<14 &gpio_pirq 4>,	/* touch_int_l (pirqm) */
127 			<15 &gpio_unused 0>,	/* unused (strap) */
128 			<16 &gpio_input 0>,	/* pch_wp */
129 			<17 &gpio_unused 0>,	/* unused */
130 			<18 &gpio_unused 0>,	/* unused */
131 			<19 &gpio_unused 0>,	/* unused */
132 			<20 &gpio_native 0>,	/* pcie_wlan_clkreq_l */
133 			<21 &gpio_out_high 0>,	/* pp3300_ssd_en */
134 			<22 &gpio_unused 0>,	/* unused */
135 			<23 &gpio_out_low 0>,	/* pp3300_autobahn_en */
136 			<24 &gpio_unused 0>,	/* unused */
137 			<25 &gpio_input 0>,	/* ec_in_rw */
138 			<26 &gpio_unused 0>,	/* unused */
139 			<27 &gpio_acpi_sci 0>,	/* pch_wake_l */
140 			<28 &gpio_unused 0>,	/* unused */
141 			<29 &gpio_unused 0>,	/* unused */
142 			<30 &gpio_native 0>,	/* native: pch_suswarn_l */
143 			<31 &gpio_native 0>,	/* native: acok_buf */
144 			<32 &gpio_native 0>,	/* native: lpc_clkrun_l */
145 			<33 &gpio_native 0>,	/* native: ssd_devslp */
146 			<34 &gpio_acpi_smi 0>,	/* ec_smi_l */
147 			<35 &gpio_acpi_smi 0>,	/* pch_nmi_dbg_l (route in nmi_en) */
148 			<36 &gpio_acpi_sci 0>,	/* ec_sci_l */
149 			<37 &gpio_unused 0>,	/* unused */
150 			<38 &gpio_unused 0>,	/* unused */
151 			<39 &gpio_unused 0>,	/* unused */
152 			<40 &gpio_native 0>,	/* native: pch_usb1_oc_l */
153 			<41 &gpio_native 0>,	/* native: pch_usb2_oc_l */
154 			<42 &gpio_unused 0>,	/* wlan_disable_l */
155 			<43 &gpio_out_high 0>,	/* pp1800_codec_en */
156 			<44 &gpio_unused 0>,	/* unused */
157 			<45 &gpio_acpi_sci 0>,	/* dsp_int - codec wake */
158 			<46 &gpio_pirq 6>,	/* hotword_det_l_3v3 (pirqo) - codec irq */
159 			<47 &gpio_out_low 0>,	/* ssd_reset_l */
160 			<48 &gpio_unused 0>,	/* unused */
161 			<49 &gpio_unused 0>,	/* unused */
162 			<50 &gpio_unused 0>,	/* unused */
163 			<51 &gpio_unused 0>,	/* unused */
164 			<52 &gpio_input 0>,	/* sim_det */
165 			<53 &gpio_unused 0>,	/* unused */
166 			<54 &gpio_unused 0>,	/* unused */
167 			<55 &gpio_unused 0>,	/* unused */
168 			<56 &gpio_unused 0>,	/* unused */
169 			<57 &gpio_out_high 0>,	/* codec_reset_l */
170 			<58 &gpio_unused 0>,	/* unused */
171 			<59 &gpio_out_high 0>,	/* lte_disable_l */
172 			<60 &gpio_unused 0>,	/* unused */
173 			<61 &gpio_native 0>,	/* native: pch_sus_stat */
174 			<62 &gpio_native 0>,	/* native: pch_susclk */
175 			<63 &gpio_native 0>,	/* native: pch_slp_s5_l */
176 			<64 &gpio_unused 0>,	/* unused */
177 			<65 &gpio_input 0>,	/* ram_id3 */
178 			<66 &gpio_input 0>,	/* ram_id3_old (strap) */
179 			<67 &gpio_input 0>,	/* ram_id0 */
180 			<68 &gpio_input 0>,	/* ram_id1 */
181 			<69 &gpio_input 0>,	/* ram_id2 */
182 			<70 &gpio_unused 0>,	/* unused */
183 			<71 &gpio_native 0>,	/* native: modphy_en */
184 			<72 &gpio_unused 0>,	/* unused */
185 			<73 &gpio_unused 0>,	/* unused */
186 			<74 &gpio_unused 0>,	/* unused */
187 			<75 &gpio_unused 0>,	/* unused */
188 			<76 &gpio_unused 0>,	/* unused */
189 			<77 &gpio_unused 0>,	/* unused */
190 			<78 &gpio_unused 0>,	/* unused */
191 			<79 &gpio_unused 0>,	/* unused */
192 			<80 &gpio_unused 0>,	/* unused */
193 			<81 &gpio_unused 0>,	/* unused */
194 			<82 &gpio_native 0>,	/* native: ec_rcin_l */
195 			<83 &gpio_native 0>,	/* gspi0_cs */
196 			<84 &gpio_native 0>,	/* gspi0_clk */
197 			<85 &gpio_native 0>,	/* gspi0_miso */
198 			<86 &gpio_native 0>,	/* gspi0_mosi (strap) */
199 			<87 &gpio_unused 0>,	/* unused */
200 			<88 &gpio_unused 0>,	/* unused */
201 			<89 &gpio_out_high 0>,	/* pp3300_sd_en */
202 			<90 &gpio_unused 0>,	/* unused */
203 			<91 &gpio_unused 0>,	/* unused */
204 			<92 &gpio_unused 0>,	/* unused */
205 			<93 &gpio_unused 0>,	/* unused */
206 			<94 &gpio_unused 0 >;	/* unused */
207 	};
208 };
209