15318f18dSGabriel HuauIntel x86 PINCTRL/GPIO controller 25318f18dSGabriel Huau 35318f18dSGabriel HuauPin-muxing on x86 can be described with a node for the PINCTRL master 45318f18dSGabriel Huaunode and a set of child nodes for each pin on the SoC. 55318f18dSGabriel Huau 65318f18dSGabriel HuauThe PINCTRL master node requires the following properties: 75318f18dSGabriel Huau- compatible : "intel,x86-pinctrl" 85318f18dSGabriel Huau 95318f18dSGabriel HuauPin nodes must be children of the pinctrl master node and can 105318f18dSGabriel Huaucontain the following properties: 11*c13dcb3dSSimon Glass- pad-offset - (required) offset in the IOBASE for the pin to configure 12*c13dcb3dSSimon Glass- gpio-offset - (required) 2 cells 13*c13dcb3dSSimon Glass - offset in the GPIOBASE for the pin to configure 14*c13dcb3dSSimon Glass - the bit shift in this register (4 = bit 4) 15*c13dcb3dSSimon Glass- mode-gpio - (optional) standalone property to force the pin into GPIO mode 16*c13dcb3dSSimon Glass- mode-func - (optional) function number to assign to the pin. If 17*c13dcb3dSSimon Glass 'mode-gpio' is set, this property will be ignored. 185318f18dSGabriel Huauin case of 'mode-gpio' property set: 19*c13dcb3dSSimon Glass- output-value - (optional) this set the default output value of the GPIO 20*c13dcb3dSSimon Glass- direction - (optional) this set the direction of the gpio 21*c13dcb3dSSimon Glass- pull-str - (optional) this set the pull strength of the pin 22*c13dcb3dSSimon Glass- pull-assign - (optional) this set the pull assignement (up/down) of the pin 237ac99be6SSimon Glass- invert - (optional) this input pin is inverted 245318f18dSGabriel Huau 255318f18dSGabriel HuauExample: 265318f18dSGabriel Huau 275318f18dSGabriel Huaupin_usb_host_en0@0 { 285318f18dSGabriel Huau gpio-offset = <0x80 8>; 295318f18dSGabriel Huau pad-offset = <0x260>; 305318f18dSGabriel Huau mode-gpio; 315318f18dSGabriel Huau output-value = <1>; 325318f18dSGabriel Huau direction = <PIN_OUTPUT>; 335318f18dSGabriel Huau}; 34