1NVIDIA Tegra Boot and Power Management Processor (BPMP)
2
3The BPMP is a specific processor in Tegra chip, which is designed for
4booting process handling and offloading the power management, clock
5management, and reset control tasks from the CPU. The binding document
6defines the resources that would be used by the BPMP firmware driver,
7which can create the interprocessor communication (IPC) between the CPU
8and BPMP.
9
10Required properties:
11- name : Should be bpmp
12- compatible
13    Array of strings
14    One of:
15    - "nvidia,tegra186-bpmp"
16- mboxes : The phandle of mailbox controller and the mailbox specifier.
17- shmem : List of the phandle of the TX and RX shared memory area that
18	  the IPC between CPU and BPMP is based on.
19- #clock-cells : Should be 1.
20- #power-domain-cells : Should be 1.
21- #reset-cells : Should be 1.
22
23This node is a mailbox consumer. See the following files for details of
24the mailbox subsystem, and the specifiers implemented by the relevant
25provider(s):
26
27- .../mailbox/mailbox.txt
28- .../mailbox/nvidia,tegra186-hsp.txt
29
30This node is a clock, power domain, and reset provider. See the following
31files for general documentation of those features, and the specifiers
32implemented by this node:
33
34- .../clock/clock-bindings.txt
35- <dt-bindings/clock/tegra186-clock.h>
36- ../power/power_domain.txt
37- <dt-bindings/power/tegra186-powergate.h>
38- .../reset/reset.txt
39- <dt-bindings/reset/tegra186-reset.h>
40
41The BPMP implements some services which must be represented by separate nodes.
42For example, it can provide access to certain I2C controllers, and the I2C
43bindings represent each I2C controller as a device tree node. Such nodes should
44be nested directly inside the main BPMP node.
45
46Software can determine whether a child node of the BPMP node represents a device
47by checking for a compatible property. Any node with a compatible property
48represents a device that can be instantiated. Nodes without a compatible
49property may be used to provide configuration information regarding the BPMP
50itself, although no such configuration nodes are currently defined by this
51binding.
52
53The BPMP firmware defines no single global name-/numbering-space for such
54services. Put another way, the numbering scheme for I2C buses is distinct from
55the numbering scheme for any other service the BPMP may provide (e.g. a future
56hypothetical SPI bus service). As such, child device nodes will have no reg
57property, and the BPMP node will have no #address-cells or #size-cells property.
58
59The shared memory bindings for BPMP
60-----------------------------------
61
62The shared memory area for the IPC TX and RX between CPU and BPMP are
63predefined and work on top of sysram, which is an SRAM inside the chip.
64
65See ".../sram/sram.txt" for the bindings.
66
67Example:
68
69hsp_top0: hsp@03c00000 {
70	...
71	#mbox-cells = <2>;
72};
73
74sysram@30000000 {
75	compatible = "nvidia,tegra186-sysram", "mmio-sram";
76	reg = <0x0 0x30000000 0x0 0x50000>;
77	#address-cells = <2>;
78	#size-cells = <2>;
79	ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
80
81	cpu_bpmp_tx: bpmp_shmem@4e000 {
82		compatible = "nvidia,tegra186-bpmp-shmem";
83		reg = <0x0 0x4e000 0x0 0x1000>;
84	};
85
86	cpu_bpmp_rx: bpmp_shmem@4f000 {
87		compatible = "nvidia,tegra186-bpmp-shmem";
88		reg = <0x0 0x4f000 0x0 0x1000>;
89	};
90};
91
92bpmp {
93	compatible = "nvidia,tegra186-bpmp";
94	mboxes = <&hsp_top0 HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>;
95	shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
96	#clock-cells = <1>;
97	#power-domain-cells = <1>;
98	#reset-cells = <1>;
99
100	i2c {
101		compatible = "...";
102		...
103	};
104};
105