1* Nios II Processor Binding
2
3This binding specifies what properties available in the device tree
4representation of a Nios II Processor Core.
5
6Users can use sopc2dts tool for generating device tree sources (dts) from a
7Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts
8
9Required properties:
10
11- compatible: Compatible property value should be "altr,nios2-1.0" or
12  "altr,nios2-1.1".
13- reg: Contains CPU index.
14- clock-frequency: Contains the clock frequency for CPU, in Hz.
15- dcache-line-size: Contains data cache line size.
16- icache-line-size: Contains instruction line size.
17- dcache-size: Contains data cache size.
18- icache-size: Contains instruction cache size.
19- altr,reset-addr: Specifies CPU reset address
20- altr,exception-addr: Specifies CPU exception address
21
22Optional properties:
23- altr,has-initda: Specifies CPU support initda instruction, should be 1.
24- altr,has-mmu: Specifies CPU support MMU support.
25- altr,has-mul: Specifies CPU hardware multipy support.
26- altr,has-div: Specifies CPU hardware divide support
27- altr,implementation: Nios II core implementation, this should be "fast";
28
29Example:
30
31cpu@0x0 {
32	device_type = "cpu";
33	compatible = "altr,nios2-1.0";
34	reg = <0>;
35	interrupt-controller;
36	#interrupt-cells = <1>;
37	clock-frequency = <125000000>;
38	dcache-line-size = <32>;
39	icache-line-size = <32>;
40	dcache-size = <32768>;
41	icache-size = <32768>;
42	altr,implementation = "fast";
43	altr,pid-num-bits = <8>;
44	altr,tlb-num-ways = <16>;
45	altr,tlb-num-entries = <128>;
46	altr,tlb-ptr-sz = <7>;
47	altr,has-div = <1>;
48	altr,has-mul = <1>;
49	altr,reset-addr = <0xc2800000>;
50	altr,fast-tlb-miss-addr = <0xc7fff400>;
51	altr,exception-addr = <0xd0000020>;
52	altr,has-initda = <1>;
53	altr,has-mmu = <1>;
54};
55