1STMicroelectronics STM32MP1 clock tree initialization
2=====================================================
3
4The STM32MP clock tree initialization is based on device tree information
5for RCC IP and on fixed clocks.
6
7-------------------------------
8RCC CLOCK = st,stm32mp1-rcc-clk
9-------------------------------
10
11The RCC IP is both a reset and a clock controller but this documentation only
12describes the fields added for clock tree initialization which are not present
13in Linux binding.
14
15Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common
16with Linux.
17
18Required properties:
19
20- compatible: Should be "st,stm32mp1-rcc-clk"
21
22- st,clksrc : The clock source in this order
23
24	for STM32MP15x: 9 clock sources are requested
25		MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
26
27	with value equals to RCC clock specifier as defined in
28	dt-bindings/clock/stm32mp1-clksrc.h: CLK_<NAME>_<SOURCE>
29
30- st,clkdiv : The div parameters in this order
31	for STM32MP15x: 11 dividers value are requested
32		MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
33
34	with DIV coding defined in RCC associated register RCC_xxxDIVR
35
36	most the case, it is:
37		0x0: not divided
38		0x1: division by 2
39		0x2: division by 4
40		0x3: division by 8
41		...
42
43	but for RTC MCO1 MCO2, the coding is different:
44		0x0: not divided
45		0x1: division by 2
46		0x2: division by 3
47		0x3: division by 4
48		...
49
50Optional Properties:
51- st,pll
52    PLL children node for PLL1 to PLL4 : (see ref manual for details)
53    with associated index 0 to 3 (st,pll@0 to st,pll@4)
54    PLLx is off when the associated node is absent
55
56    - Sub-nodes:
57
58	- cfg:	The parameters for PLL configuration in this order:
59		DIVM DIVN DIVP DIVQ DIVR Output
60
61		with DIV value as defined in RCC spec:
62			0x0: bypass (division by 1)
63			0x1: division by 2
64			0x2: division by 3
65			0x3: division by 4
66			...
67
68		and Output = bitfield for each output value = 1:ON/0:OFF
69			BIT(0) => output P : DIVPEN
70			BIT(1) => output Q : DIVQEN
71			BIT(2) => output R : DIVREN
72		  NB : macro PQR(p,q,r) can be used to build this value
73		       with p,p,r = 0 or 1
74
75	- frac : Fractional part of the multiplication factor
76		(optional, PLL is in integer mode when absent)
77
78	- csg : Clock Spreading Generator (optional)
79	        with parameters in this order:
80		MOD_PER INC_STEP SSCG_MODE
81
82		* MOD_PER: Modulation Period Adjustment
83		* INC_STEP: Modulation Depth Adjustment
84		* SSCG_MODE: Spread spectrum clock generator mode
85		  you can use associated defines from stm32mp1-clksrc.h
86		  * SSCG_MODE_CENTER_SPREAD = 0
87		  * SSCG_MODE_DOWN_SPREAD = 1
88
89
90- st,pkcs : used to configure the peripherals kernel clock selection
91  containing a list of peripheral kernel clock source identifier as defined
92  in the file dt-bindings/clock/stm32mp1-clksrc.h
93
94  Example:
95
96	rcc: rcc@50000000 {
97		compatible = "syscon", "simple-mfd";
98
99		reg = <0x50000000 0x1000>;
100
101		rcc_clk: rcc-clk@50000000 {
102			#clock-cells = <1>;
103			compatible = "st,stm32mp1-rcc-clk";
104
105			st,clksrc = <	CLK_MPU_PLL1P
106					CLK_AXI_PLL2P
107					CLK_MCU_HSI
108					CLK_PLL12_HSE
109					CLK_PLL3_HSE
110					CLK_PLL4_HSE
111					CLK_RTC_HSE
112					CLK_MCO1_DISABLED
113					CLK_MCO2_DISABLED
114			>;
115
116			st,clkdiv = <
117				1 /*MPU*/
118				0 /*AXI*/
119				0 /*MCU*/
120				1 /*APB1*/
121				1 /*APB2*/
122				1 /*APB3*/
123				1 /*APB4*/
124				5 /*APB5*/
125				23 /*RTC*/
126				0 /*MCO1*/
127				0 /*MCO2*/
128			>;
129
130			st,pll@0 {
131				cfg = < 1 53 0 0 0 1 >;
132				frac = < 0x810 >;
133			};
134			st,pll@1 {
135				cfg = < 1 43 1 0 0 PQR(0,1,1) >;
136				csg = < 10 20 1 >;
137			};
138			st,pll@2 {
139				cfg = < 2 85 3 13 3 0 >;
140				csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
141			};
142			st,pll@3 {
143				cfg = < 2 78 4 7 9 3 >;
144			};
145			st,pkcs = <
146					CLK_STGEN_HSE
147					CLK_CKPER_HSI
148					CLK_USBPHY_PLL2P
149					CLK_DSI_PLL2Q
150				  >;
151		};
152	};
153
154--------------------------
155other clocks = fixed-clock
156--------------------------
157The clock tree is also based on 5 fixed-clock in clocks node
158used to define the state of associated ST32MP1 oscillators:
159- clk-lsi
160- clk-lse
161- clk-hsi
162- clk-hse
163- clk-csi
164
165At boot the clock tree initialization will
166- enable the oscillator present in device tree
167- disable HSI oscillator if the node is absent (always activated by bootrom)
168
169Optional properties :
170
171a) for external oscillator: "clk-lse", "clk-hse"
172
173	4 optional fields are managed
174	- "st,bypass" Configure the oscillator bypass mode (HSEBYP, LSEBYP)
175	- "st,digbypass" Configure the bypass mode as full-swing digital signal
176	  (DIGBYP)
177	- "st,css" Activate the clock security system (HSECSSON, LSECSSON)
178	- "st,drive" (only for LSE) value of the drive for the oscillator
179	   (see LSEDRV_ define in the file dt-bindings/clock/stm32mp1-clksrc.h)
180
181	Example board file:
182
183	/ {
184		clocks {
185			clk_hse: clk-hse {
186				#clock-cells = <0>;
187				compatible = "fixed-clock";
188				clock-frequency = <64000000>;
189				st,bypass;
190			};
191
192			clk_lse: clk-lse {
193				#clock-cells = <0>;
194				compatible = "fixed-clock";
195				clock-frequency = <32768>;
196				st,css;
197				st,drive = <LSEDRV_LOWEST>;
198			};
199	};
200
201b) for internal oscillator: "clk-hsi"
202
203	internally HSI clock is fixed to 64MHz for STM32MP157 soc
204	in device tree clk-hsi is the clock after HSIDIV (ck_hsi in RCC doc)
205	So this clock frequency is used to compute the expected HSI_DIV
206	for the clock tree initialisation
207
208	ex: for HSIDIV = /1
209
210	/ {
211		clocks {
212			clk_hsi: clk-hsi {
213				#clock-cells = <0>;
214				compatible = "fixed-clock";
215				clock-frequency = <64000000>;
216			};
217	};
218
219	ex: for HSIDIV = /2
220
221	/ {
222		clocks {
223			clk_hsi: clk-hsi {
224				#clock-cells = <0>;
225				compatible = "fixed-clock";
226				clock-frequency = <32000000>;
227			};
228	};
229