1STMicroelectronics STM32H7 Reset and Clock Controller
2=====================================================
3
4The RCC IP is both a reset and a clock controller.
5
6Please refer to clock-bindings.txt for common clock controller binding usage.
7Please also refer to reset.txt for common reset controller binding usage.
8
9Required properties:
10- compatible: Should be:
11  "st,stm32h743-rcc"
12
13- reg: should be register base and length as documented in the
14  datasheet
15
16- #reset-cells: 1, see below
17
18- #clock-cells : from common clock binding; shall be set to 1
19
20- clocks: External oscillator clock phandle
21  - high speed external clock signal (HSE)
22  - low speed external clock signal (LSE)
23  - external I2S clock (I2S_CKIN)
24
25- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
26  write protection (RTC clock).
27
28- pll x node: Allow to register a pll with specific parameters.
29  Please see PLL section below.
30
31Example:
32
33	rcc: rcc@58024400 {
34		#reset-cells = <1>;
35		#clock-cells = <2>
36		compatible = "st,stm32h743-rcc", "st,stm32-rcc";
37		reg = <0x58024400 0x400>;
38		clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
39
40		st,syscfg = <&pwrcfg>;
41
42		#address-cells = <1>;
43		#size-cells = <0>;
44
45		vco1@58024430 {
46			#clock-cells = <0>;
47			compatible = "stm32,pll";
48			reg = <0>;
49		};
50
51		vco2@58024438 {
52			#clock-cells = <0>;
53			compatible = "stm32,pll";
54			reg = <1>;
55			st,clock-div = <2>;
56			st,clock-mult = <40>;
57			st,frac-status = <0>;
58			st,frac = <0>;
59			st,vcosel = <1>;
60			st,pllrge = <2>;
61		};
62	};
63
64
65STM32H7 PLL
66-----------
67
68The VCO of STM32 PLL could be reprensented like this:
69
70  Vref    ---------       --------
71    ---->| / DIVM  |---->| x DIVN | ------> VCO
72          ---------       --------
73		             ^
74			     |
75	                  -------
76		         | FRACN |
77		          -------
78
79When the PLL is configured in integer mode:
80- VCO = ( Vref / DIVM ) * DIVN
81
82When the PLL is configured in fractional mode:
83- VCO = ( Vref / DIVM ) * ( DIVN + FRACN / 2^13)
84
85
86Required properties for pll node:
87- compatible: Should be:
88  "stm32,pll"
89
90- #clock-cells: from common clock binding; shall be set to 0
91- reg: Should be the pll number.
92
93Optional properties:
94- st,clock-div:  DIVM division factor       : <1..63>
95- st,clock-mult: DIVN multiplication factor : <4..512>
96
97- st,frac-status:
98   - 0 Pll is configured in integer mode
99   - 1 Pll is configure in fractional mode
100
101- st,frac: Fractional part of the multiplication factor : <0..8191>
102
103- st,vcosel: VCO selection
104  - 0: Wide VCO range:192 to 836 MHz
105  - 1: Medium VCO range:150 to 420 MHz
106
107- st,pllrge: PLL input frequency range
108  - 0: The PLL input (Vref / DIVM) clock range frequency is between 1 and 2 MHz
109  - 1: The PLL input (Vref / DIVM) clock range frequency is between 2 and 4 MHz
110  - 2: The PLL input (Vref / DIVM) clock range frequency is between 4 and 8 MHz
111  - 3: The PLL input (Vref / DIVM) clock range frequency is between 8 and 16 MHz
112
113
114The peripheral clock consumer should specify the desired clock by
115having the clock ID in its "clocks" phandle cell.
116
117All available clocks are defined as preprocessor macros in
118dt-bindings/clock/stm32h7-clks.h header and can be used in device
119tree sources.
120
121Example:
122
123		timer5: timer@40000c00 {
124			compatible = "st,stm32-timer";
125			reg = <0x40000c00 0x400>;
126			interrupts = <50>;
127			clocks = <&rcc TIM5_CK>;
128
129		};
130
131Specifying softreset control of devices
132=======================================
133
134Device nodes should specify the reset channel required in their "resets"
135property, containing a phandle to the reset device node and an index specifying
136which channel to use.
137The index is the bit number within the RCC registers bank, starting from RCC
138base address.
139It is calculated as: index = register_offset / 4 * 32 + bit_offset.
140Where bit_offset is the bit offset within the register.
141
142For example, for CRC reset:
143  crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
144
145All available preprocessor macros for reset are defined dt-bindings//mfd/stm32h7-rcc.h
146header and can be used in device tree sources.
147
148example:
149
150	timer2 {
151		resets	= <&rcc STM32H7_APB1L_RESET(TIM2)>;
152	};
153