1STMicroelectronics STM32 Reset and Clock Controller
2===================================================
3
4The RCC IP is both a reset and a clock controller.
5
6Please refer to clock-bindings.txt for common clock controller binding usage.
7Please also refer to reset.txt for common reset controller binding usage.
8
9Required properties:
10- compatible: Should be:
11  "st,stm32f42xx-rcc"
12  "st,stm32f469-rcc"
13- reg: should be register base and length as documented in the
14  datasheet
15- #reset-cells: 1, see below
16- #clock-cells: 2, device nodes should specify the clock in their "clocks"
17  property, containing a phandle to the clock device node, an index selecting
18  between gated clocks and other clocks and an index specifying the clock to
19  use.
20
21Example:
22
23	rcc: rcc@40023800 {
24		#reset-cells = <1>;
25		#clock-cells = <2>
26		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
27		reg = <0x40023800 0x400>;
28	};
29
30Specifying gated clocks
31=======================
32
33The primary index must be set to 0.
34
35The secondary index is the bit number within the RCC register bank, starting
36from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
37
38It is calculated as: index = register_offset / 4 * 32 + bit_offset.
39Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
40
41To simplify the usage and to share bit definition with the reset and clock
42drivers of the RCC IP, macros are available to generate the index in
43human-readble format.
44
45For STM32F4 series, the macro are available here:
46 - include/dt-bindings/mfd/stm32f4-rcc.h
47
48Example:
49
50	/* Gated clock, AHB1 bit 0 (GPIOA) */
51	... {
52		clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
53	};
54
55	/* Gated clock, AHB2 bit 4 (CRYP) */
56	... {
57		clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
58	};
59
60Specifying other clocks
61=======================
62
63The primary index must be set to 1.
64
65The secondary index is bound with the following magic numbers:
66
67	0	SYSTICK
68	1	FCLK
69
70Example:
71
72	/* Misc clock, FCLK */
73	... {
74		clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
75	};
76
77
78Specifying softreset control of devices
79=======================================
80
81Device nodes should specify the reset channel required in their "resets"
82property, containing a phandle to the reset device node and an index specifying
83which channel to use.
84The index is the bit number within the RCC registers bank, starting from RCC
85base address.
86It is calculated as: index = register_offset / 4 * 32 + bit_offset.
87Where bit_offset is the bit offset within the register.
88For example, for CRC reset:
89  crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
90
91example:
92
93	timer2 {
94		resets	= <&rcc STM32F4_APB1_RESET(TIM2)>;
95	};
96