1*266fa4dfSPatrick DelaunaySTMicroelectronics STM32MP1 clock tree initialization 2*266fa4dfSPatrick Delaunay===================================================== 3*266fa4dfSPatrick Delaunay 4*266fa4dfSPatrick DelaunayThe STM32MP clock tree initialization is based on device tree information 5*266fa4dfSPatrick Delaunayfor RCC IP and on fixed clocks. 6*266fa4dfSPatrick Delaunay 7*266fa4dfSPatrick Delaunay------------------------------- 8*266fa4dfSPatrick DelaunayRCC CLOCK = st,stm32mp1-rcc-clk 9*266fa4dfSPatrick Delaunay------------------------------- 10*266fa4dfSPatrick Delaunay 11*266fa4dfSPatrick DelaunayThe RCC IP is both a reset and a clock controller but this documentation only 12*266fa4dfSPatrick Delaunaydescribes the fields added for clock tree initialization which are not present 13*266fa4dfSPatrick Delaunayin Linux binding. 14*266fa4dfSPatrick Delaunay 15*266fa4dfSPatrick DelaunayPlease refer to ../mfd/st,stm32-rcc.txt for all the other properties common 16*266fa4dfSPatrick Delaunaywith Linux. 17*266fa4dfSPatrick Delaunay 18*266fa4dfSPatrick DelaunayRequired properties: 19*266fa4dfSPatrick Delaunay 20*266fa4dfSPatrick Delaunay- compatible: Should be "st,stm32mp1-rcc-clk" 21*266fa4dfSPatrick Delaunay 22*266fa4dfSPatrick Delaunay- st,clksrc : The clock source in this order 23*266fa4dfSPatrick Delaunay 24*266fa4dfSPatrick Delaunay for STM32MP15x: 9 clock sources are requested 25*266fa4dfSPatrick Delaunay MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2 26*266fa4dfSPatrick Delaunay 27*266fa4dfSPatrick Delaunay with value equals to RCC clock specifier as defined in 28*266fa4dfSPatrick Delaunay dt-bindings/clock/stm32mp1-clksrc.h: CLK_<NAME>_<SOURCE> 29*266fa4dfSPatrick Delaunay 30*266fa4dfSPatrick Delaunay- st,clkdiv : The div parameters in this order 31*266fa4dfSPatrick Delaunay for STM32MP15x: 11 dividers value are requested 32*266fa4dfSPatrick Delaunay MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2 33*266fa4dfSPatrick Delaunay 34*266fa4dfSPatrick Delaunay with DIV coding defined in RCC associated register RCC_xxxDIVR 35*266fa4dfSPatrick Delaunay 36*266fa4dfSPatrick Delaunay most the case, it is: 37*266fa4dfSPatrick Delaunay 0x0: not divided 38*266fa4dfSPatrick Delaunay 0x1: division by 2 39*266fa4dfSPatrick Delaunay 0x2: division by 4 40*266fa4dfSPatrick Delaunay 0x3: division by 8 41*266fa4dfSPatrick Delaunay ... 42*266fa4dfSPatrick Delaunay 43*266fa4dfSPatrick Delaunay but for RTC MCO1 MCO2, the coding is different: 44*266fa4dfSPatrick Delaunay 0x0: not divided 45*266fa4dfSPatrick Delaunay 0x1: division by 2 46*266fa4dfSPatrick Delaunay 0x2: division by 3 47*266fa4dfSPatrick Delaunay 0x3: division by 4 48*266fa4dfSPatrick Delaunay ... 49*266fa4dfSPatrick Delaunay 50*266fa4dfSPatrick DelaunayOptional Properties: 51*266fa4dfSPatrick Delaunay- st,pll 52*266fa4dfSPatrick Delaunay PLL children node for PLL1 to PLL4 : (see ref manual for details) 53*266fa4dfSPatrick Delaunay with associated index 0 to 3 (st,pll@0 to st,pll@4) 54*266fa4dfSPatrick Delaunay PLLx is off when the associated node is absent 55*266fa4dfSPatrick Delaunay 56*266fa4dfSPatrick Delaunay - Sub-nodes: 57*266fa4dfSPatrick Delaunay 58*266fa4dfSPatrick Delaunay - cfg: The parameters for PLL configuration in this order: 59*266fa4dfSPatrick Delaunay DIVM DIVN DIVP DIVQ DIVR Output 60*266fa4dfSPatrick Delaunay 61*266fa4dfSPatrick Delaunay with DIV value as defined in RCC spec: 62*266fa4dfSPatrick Delaunay 0x0: bypass (division by 1) 63*266fa4dfSPatrick Delaunay 0x1: division by 2 64*266fa4dfSPatrick Delaunay 0x2: division by 3 65*266fa4dfSPatrick Delaunay 0x3: division by 4 66*266fa4dfSPatrick Delaunay ... 67*266fa4dfSPatrick Delaunay 68*266fa4dfSPatrick Delaunay and Output = bitfield for each output value = 1:ON/0:OFF 69*266fa4dfSPatrick Delaunay BIT(0) => output P : DIVPEN 70*266fa4dfSPatrick Delaunay BIT(1) => output Q : DIVQEN 71*266fa4dfSPatrick Delaunay BIT(2) => output R : DIVREN 72*266fa4dfSPatrick Delaunay NB : macro PQR(p,q,r) can be used to build this value 73*266fa4dfSPatrick Delaunay with p,p,r = 0 or 1 74*266fa4dfSPatrick Delaunay 75*266fa4dfSPatrick Delaunay - frac : Fractional part of the multiplication factor 76*266fa4dfSPatrick Delaunay (optional, PLL is in integer mode when absent) 77*266fa4dfSPatrick Delaunay 78*266fa4dfSPatrick Delaunay - csg : Clock Spreading Generator (optional) 79*266fa4dfSPatrick Delaunay with parameters in this order: 80*266fa4dfSPatrick Delaunay MOD_PER INC_STEP SSCG_MODE 81*266fa4dfSPatrick Delaunay 82*266fa4dfSPatrick Delaunay * MOD_PER: Modulation Period Adjustment 83*266fa4dfSPatrick Delaunay * INC_STEP: Modulation Depth Adjustment 84*266fa4dfSPatrick Delaunay * SSCG_MODE: Spread spectrum clock generator mode 85*266fa4dfSPatrick Delaunay you can use associated defines from stm32mp1-clksrc.h 86*266fa4dfSPatrick Delaunay * SSCG_MODE_CENTER_SPREAD = 0 87*266fa4dfSPatrick Delaunay * SSCG_MODE_DOWN_SPREAD = 1 88*266fa4dfSPatrick Delaunay 89*266fa4dfSPatrick Delaunay 90*266fa4dfSPatrick Delaunay- st,pkcs : used to configure the peripherals kernel clock selection 91*266fa4dfSPatrick Delaunay containing a list of peripheral kernel clock source identifier as defined 92*266fa4dfSPatrick Delaunay in the file dt-bindings/clock/stm32mp1-clksrc.h 93*266fa4dfSPatrick Delaunay 94*266fa4dfSPatrick Delaunay Example: 95*266fa4dfSPatrick Delaunay 96*266fa4dfSPatrick Delaunay rcc: rcc@50000000 { 97*266fa4dfSPatrick Delaunay compatible = "syscon", "simple-mfd"; 98*266fa4dfSPatrick Delaunay 99*266fa4dfSPatrick Delaunay reg = <0x50000000 0x1000>; 100*266fa4dfSPatrick Delaunay 101*266fa4dfSPatrick Delaunay rcc_clk: rcc-clk@50000000 { 102*266fa4dfSPatrick Delaunay #clock-cells = <1>; 103*266fa4dfSPatrick Delaunay compatible = "st,stm32mp1-rcc-clk"; 104*266fa4dfSPatrick Delaunay 105*266fa4dfSPatrick Delaunay st,clksrc = < CLK_MPU_PLL1P 106*266fa4dfSPatrick Delaunay CLK_AXI_PLL2P 107*266fa4dfSPatrick Delaunay CLK_MCU_HSI 108*266fa4dfSPatrick Delaunay CLK_PLL12_HSE 109*266fa4dfSPatrick Delaunay CLK_PLL3_HSE 110*266fa4dfSPatrick Delaunay CLK_PLL4_HSE 111*266fa4dfSPatrick Delaunay CLK_RTC_HSE 112*266fa4dfSPatrick Delaunay CLK_MCO1_DISABLED 113*266fa4dfSPatrick Delaunay CLK_MCO2_DISABLED 114*266fa4dfSPatrick Delaunay >; 115*266fa4dfSPatrick Delaunay 116*266fa4dfSPatrick Delaunay st,clkdiv = < 117*266fa4dfSPatrick Delaunay 1 /*MPU*/ 118*266fa4dfSPatrick Delaunay 0 /*AXI*/ 119*266fa4dfSPatrick Delaunay 0 /*MCU*/ 120*266fa4dfSPatrick Delaunay 1 /*APB1*/ 121*266fa4dfSPatrick Delaunay 1 /*APB2*/ 122*266fa4dfSPatrick Delaunay 1 /*APB3*/ 123*266fa4dfSPatrick Delaunay 1 /*APB4*/ 124*266fa4dfSPatrick Delaunay 5 /*APB5*/ 125*266fa4dfSPatrick Delaunay 23 /*RTC*/ 126*266fa4dfSPatrick Delaunay 0 /*MCO1*/ 127*266fa4dfSPatrick Delaunay 0 /*MCO2*/ 128*266fa4dfSPatrick Delaunay >; 129*266fa4dfSPatrick Delaunay 130*266fa4dfSPatrick Delaunay st,pll@0 { 131*266fa4dfSPatrick Delaunay cfg = < 1 53 0 0 0 1 >; 132*266fa4dfSPatrick Delaunay frac = < 0x810 >; 133*266fa4dfSPatrick Delaunay }; 134*266fa4dfSPatrick Delaunay st,pll@1 { 135*266fa4dfSPatrick Delaunay cfg = < 1 43 1 0 0 PQR(0,1,1)>; 136*266fa4dfSPatrick Delaunay csg = <10 20 1>; 137*266fa4dfSPatrick Delaunay }; 138*266fa4dfSPatrick Delaunay st,pll@2 { 139*266fa4dfSPatrick Delaunay cfg = < 2 85 3 13 3 0>; 140*266fa4dfSPatrick Delaunay csg = <10 20 SSCG_MODE_CENTER_SPREAD>; 141*266fa4dfSPatrick Delaunay }; 142*266fa4dfSPatrick Delaunay st,pll@3 { 143*266fa4dfSPatrick Delaunay cfg = < 2 78 4 7 9 3>; 144*266fa4dfSPatrick Delaunay }; 145*266fa4dfSPatrick Delaunay st,pkcs = < 146*266fa4dfSPatrick Delaunay CLK_STGEN_HSE 147*266fa4dfSPatrick Delaunay CLK_CKPER_HSI 148*266fa4dfSPatrick Delaunay CLK_USBPHY_PLL2P 149*266fa4dfSPatrick Delaunay CLK_DSI_PLL2Q 150*266fa4dfSPatrick Delaunay >; 151*266fa4dfSPatrick Delaunay }; 152*266fa4dfSPatrick Delaunay }; 153*266fa4dfSPatrick Delaunay 154*266fa4dfSPatrick Delaunay-------------------------- 155*266fa4dfSPatrick Delaunayother clocks = fixed-clock 156*266fa4dfSPatrick Delaunay-------------------------- 157*266fa4dfSPatrick DelaunayThe clock tree is also based on 5 fixed-clock in clocks node 158*266fa4dfSPatrick Delaunayused to define the state of associated ST32MP1 oscillators: 159*266fa4dfSPatrick Delaunay- clk-lsi 160*266fa4dfSPatrick Delaunay- clk-lse 161*266fa4dfSPatrick Delaunay- clk-hsi 162*266fa4dfSPatrick Delaunay- clk-hse 163*266fa4dfSPatrick Delaunay- clk-csi 164*266fa4dfSPatrick Delaunay 165*266fa4dfSPatrick DelaunayAt boot the clock tree initialization will 166*266fa4dfSPatrick Delaunay- enable the oscillator present in device tree 167*266fa4dfSPatrick Delaunay- disable HSI oscillator if the node is absent (always activated by bootrom) 168*266fa4dfSPatrick Delaunay 169*266fa4dfSPatrick DelaunayOptional properties : 170*266fa4dfSPatrick Delaunay 171*266fa4dfSPatrick Delaunaya) for external oscillator: "clk-lse", "clk-hse" 172*266fa4dfSPatrick Delaunay 173*266fa4dfSPatrick Delaunay 3 optional fields are managed 174*266fa4dfSPatrick Delaunay - "st,bypass" Configure the oscillator bypass mode (HSEBYP, LSEBYP) 175*266fa4dfSPatrick Delaunay - "st,css" Activate the clock security system (HSECSSON, LSECSSON) 176*266fa4dfSPatrick Delaunay - "st,drive" (only for LSE) value of the drive for the oscillator 177*266fa4dfSPatrick Delaunay (see LSEDRV_ define in the file dt-bindings/clock/stm32mp1-clksrc.h) 178*266fa4dfSPatrick Delaunay 179*266fa4dfSPatrick Delaunay Example board file: 180*266fa4dfSPatrick Delaunay 181*266fa4dfSPatrick Delaunay / { 182*266fa4dfSPatrick Delaunay clocks { 183*266fa4dfSPatrick Delaunay clk_hse: clk-hse { 184*266fa4dfSPatrick Delaunay #clock-cells = <0>; 185*266fa4dfSPatrick Delaunay compatible = "fixed-clock"; 186*266fa4dfSPatrick Delaunay clock-frequency = <64000000>; 187*266fa4dfSPatrick Delaunay st,bypass; 188*266fa4dfSPatrick Delaunay }; 189*266fa4dfSPatrick Delaunay 190*266fa4dfSPatrick Delaunay clk_lse: clk-lse { 191*266fa4dfSPatrick Delaunay #clock-cells = <0>; 192*266fa4dfSPatrick Delaunay compatible = "fixed-clock"; 193*266fa4dfSPatrick Delaunay clock-frequency = <32768>; 194*266fa4dfSPatrick Delaunay st,css; 195*266fa4dfSPatrick Delaunay st,drive = <LSEDRV_LOWEST>; 196*266fa4dfSPatrick Delaunay }; 197*266fa4dfSPatrick Delaunay }; 198*266fa4dfSPatrick Delaunay 199*266fa4dfSPatrick Delaunayb) for internal oscillator: "clk-hsi" 200*266fa4dfSPatrick Delaunay 201*266fa4dfSPatrick Delaunay internally HSI clock is fixed to 64MHz for STM32MP157 soc 202*266fa4dfSPatrick Delaunay in device tree clk-hsi is the clock after HSIDIV (ck_hsi in RCC doc) 203*266fa4dfSPatrick Delaunay So this clock frequency is used to compute the expected HSI_DIV 204*266fa4dfSPatrick Delaunay for the clock tree initialisation 205*266fa4dfSPatrick Delaunay 206*266fa4dfSPatrick Delaunay ex: for HSIDIV = /1 207*266fa4dfSPatrick Delaunay 208*266fa4dfSPatrick Delaunay / { 209*266fa4dfSPatrick Delaunay clocks { 210*266fa4dfSPatrick Delaunay clk_hsi: clk-hsi { 211*266fa4dfSPatrick Delaunay #clock-cells = <0>; 212*266fa4dfSPatrick Delaunay compatible = "fixed-clock"; 213*266fa4dfSPatrick Delaunay clock-frequency = <64000000>; 214*266fa4dfSPatrick Delaunay }; 215*266fa4dfSPatrick Delaunay }; 216*266fa4dfSPatrick Delaunay 217*266fa4dfSPatrick Delaunay ex: for HSIDIV = /2 218*266fa4dfSPatrick Delaunay 219*266fa4dfSPatrick Delaunay / { 220*266fa4dfSPatrick Delaunay clocks { 221*266fa4dfSPatrick Delaunay clk_hsi: clk-hsi { 222*266fa4dfSPatrick Delaunay #clock-cells = <0>; 223*266fa4dfSPatrick Delaunay compatible = "fixed-clock"; 224*266fa4dfSPatrick Delaunay clock-frequency = <32000000>; 225*266fa4dfSPatrick Delaunay }; 226*266fa4dfSPatrick Delaunay }; 227