1Device Tree Clock bindings for arch-rockchip
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7== Gate clocks ==
8
9These bindings are deprecated!
10Please use the soc specific CRU bindings instead.
11
12The gate registers form a continuos block which makes the dt node
13structure a matter of taste, as either all gates can be put into
14one gate clock spanning all registers or they can be divided into
15the 10 individual gates containing 16 clocks each.
16The code supports both approaches.
17
18Required properties:
19- compatible : "rockchip,rk2928-gate-clk"
20- reg : shall be the control register address(es) for the clock.
21- #clock-cells : from common clock binding; shall be set to 1
22- clock-output-names : the corresponding gate names that the clock controls
23- clocks : should contain the parent clock for each individual gate,
24  therefore the number of clocks elements should match the number of
25  clock-output-names
26
27Example using multiple gate clocks:
28
29		clk_gates0: gate-clk@200000d0 {
30			compatible = "rockchip,rk2928-gate-clk";
31			reg = <0x200000d0 0x4>;
32			clocks = <&dummy>, <&dummy>,
33				 <&dummy>, <&dummy>,
34				 <&dummy>, <&dummy>,
35				 <&dummy>, <&dummy>,
36				 <&dummy>, <&dummy>,
37				 <&dummy>, <&dummy>,
38				 <&dummy>, <&dummy>,
39				 <&dummy>, <&dummy>;
40
41			clock-output-names =
42				"gate_core_periph", "gate_cpu_gpll",
43				"gate_ddrphy", "gate_aclk_cpu",
44				"gate_hclk_cpu", "gate_pclk_cpu",
45				"gate_atclk_cpu", "gate_i2s0",
46				"gate_i2s0_frac", "gate_i2s1",
47				"gate_i2s1_frac", "gate_i2s2",
48				"gate_i2s2_frac", "gate_spdif",
49				"gate_spdif_frac", "gate_testclk";
50
51			#clock-cells = <1>;
52		};
53
54		clk_gates1: gate-clk@200000d4 {
55			compatible = "rockchip,rk2928-gate-clk";
56			reg = <0x200000d4 0x4>;
57			clocks = <&xin24m>, <&xin24m>,
58				 <&xin24m>, <&dummy>,
59				 <&dummy>, <&xin24m>,
60				 <&xin24m>, <&dummy>,
61				 <&xin24m>, <&dummy>,
62				 <&xin24m>, <&dummy>,
63				 <&xin24m>, <&dummy>,
64				 <&xin24m>, <&dummy>;
65
66			clock-output-names =
67				"gate_timer0", "gate_timer1",
68				"gate_timer2", "gate_jtag",
69				"gate_aclk_lcdc1_src", "gate_otgphy0",
70				"gate_otgphy1", "gate_ddr_gpll",
71				"gate_uart0", "gate_frac_uart0",
72				"gate_uart1", "gate_frac_uart1",
73				"gate_uart2", "gate_frac_uart2",
74				"gate_uart3", "gate_frac_uart3";
75
76			#clock-cells = <1>;
77		};
78