1Rockchip Dynamic Memory Controller Driver
2Required properties:
3- compatible: "rockchip,rk3288-dmc", "syscon"
4- rockchip,cru: this driver should access cru regs, so need get cru here
5- rockchip,grf: this driver should access grf regs, so need get grf here
6- rockchip,pmu: this driver should access pmu regs, so need get pmu here
7- rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
8- rockchip,noc: this driver should access noc regs, so need get noc here
9- reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address
10- clock: must include clock specifiers corresponding to entries in the clock-names property.
11- clock-output-names: from common clock binding to override the default output clock name
12    Must contain
13      pclk_ddrupctl0: support clock for access protocol controller registers of channel 0
14      pclk_publ0: support clock for access phy controller registers of channel 0
15      pclk_ddrupctl1: support clock for access protocol controller registers of channel 1
16      pclk_publ1: support clock for access phy controller registers of channel 1
17      arm_clk: for get arm frequency
18-logic-supply: this driver should adjust VDD_LOGIC according to dmc frequency, so need get logic-supply here
19-timings:
20    Must contain
21      rockchip,odt-disable-freq: if ddr clock frequency low than odt-disable-freq,this driver should disable DDR ODT
22      rockchip,dll-disable-freq: if ddr clock frequency low than dll-disable-freq,this driver should disable DDR DLL
23      rockchip,sr-enable-freq: if ddr clock frequency high than sr-enable-freq,this driver should enable the automatic self refresh function
24      rockchip,pd-enable-freq: if ddr clock frequency high than pd-enable-freq,this driver should enable the automatic power down function
25      rockchip,auto-self-refresh-cnt: Self Refresh idle period. Memories are placed into Self-Refresh mode if the NIF is idle in Access state for auto-self-refresh-cnt * 32 * n_clk cycles.The automatic self refresh function is disabled when auto-self-refresh-cnt=0.
26      rockchip,auto-power-down-cnt: Power-down idle period. Memories are placed into power-down mode if the NIF is idle for auto-power-down-cnt n_clk cycles.The automatic power down function is disabled when auto-power-down-cnt=0.
27      rockchip,ddr-speed-bin: DDR3 type,AC timing parameters from the memory data-sheet
28        0.DDR3_800D (5-5-5)
29        1.DDR3_800E (6-6-6)
30        2.DDR3_1066E (6-6-6)
31        3.DDR3_1066F (7-7-7)
32        4.DDR3_1066G (8-8-8)
33        5.DDR3_1333F (7-7-7)
34        6.DDR3_1333G (8-8-8)
35        7.DDR3_1333H (9-9-9)
36        8.DDR3_1333J (10-10-10)
37        9.DDR3_1600G (8-8-8)
38        10.DDR3_1600H (9-9-9)
39        11.DDR3_1600J (10-10-10)
40        12.DDR3_1600K (11-11-11)
41        13.DDR3_1866J (10-10-10)
42        14.DDR3_1866K (11-11-11)
43        15.DDR3_1866L (12-12-12)
44        16.DDR3_1866M (13-13-13)
45        17.DDR3_2133K (11-11-11)
46        18.DDR3_2133L (12-12-12)
47        19.DDR3_2133M (13-13-13)
48        20.DDR3_2133N (14-14-14)
49        21.DDR3_DEFAULT
50      rockchip,trcd: tRCD,AC timing parameters from the memory data-sheet
51      rockchip,trp: tRP,AC timing parameters from the memory data-sheet
52-rockchip,num-channels: number of SDRAM channels (1 or 2)
53-rockchip,pctl-timing: parameters for the SDRAM setup, in this order:
54	togcnt1u
55	tinit
56	trsth
57	togcnt100n
58	trefi
59	tmrd
60	trfc
61	trp
62	trtw
63	tal
64	tcl
65	tcwl
66	tras
67	trc
68	trcd
69	trrd
70	trtp
71	twr
72	twtr
73	texsr
74	txp
75	txpdll
76	tzqcs
77	tzqcsi
78	tdqs
79	tcksre
80	tcksrx
81	tcke
82	tmod
83	trstl
84	tzqcl
85	tmrr
86	tckesr
87	tdpd
88-rockchip,phy-timing: PHY timing information in this order:
89	dtpr0
90	dtpr1
91	dtpr2
92	mr0..mr3
93-rockchip,sdram-channel: SDRAM channel information, each 8 bits. Both channels
94will be set up the same. The parameters are in this order:
95	rank
96	col
97	bk
98	bw
99	dbw
100	row_3_4
101	cs0_row
102	cs1_row
103- rockchip,sdram-params: SDRAM base parameters, in this order:
104	NOC timing	- value for ddrtiming register
105	NOC activate	- value for activate register
106	ddrconf		- value for ddrconf register
107	DDR frequency in MHz
108	DRAM type (3=DDR3, 6=LPDDR3)
109	stride		- stride value for soc_con2 register
110	odt             - 1 to enable DDR ODT, 0 to disable
111
112Example:
113	dmc: dmc@ff610000 {
114		compatible = "rockchip,rk3288-dmc", "syscon";
115		rockchip,cru = <&cru>;
116		rockchip,grf = <&grf>;
117		rockchip,pmu = <&pmu>;
118		rockchip,sgrf = <&sgrf>;
119		rockchip,noc = <&noc>;
120		reg = <0xff610000 0x3fc
121		       0xff620000 0x294
122		       0xff630000 0x3fc
123		       0xff640000 0x294>;
124		clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
125			 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
126			 <&cru ARMCLK>;
127		clock-names = "pclk_ddrupctl0", "pclk_publ0",
128			      "pclk_ddrupctl1", "pclk_publ1",
129			      "arm_clk";
130	};
131
132	&dmc {
133		logic-supply = <&vdd_logic>;
134		timings {
135			rockchip,odt-disable-freq = <333000000>;
136			rockchip,dll-disable-freq = <333000000>;
137			rockchip,sr-enable-freq = <333000000>;
138			rockchip,pd-enable-freq = <666000000>;
139			rockchip,auto-self-refresh-cnt = <0>;
140			rockchip,auto-power-down-cnt = <64>;
141			rockchip,ddr-speed-bin = <21>;
142			rockchip,trcd = <10>;
143			rockchip,trp = <10>;
144		};
145		rockchip,num-channels = <2>;
146		rockchip,pctl-timing = <0x29a 0x1f4 0xc8 0x42 0x4e 0x4 0xea 0xa
147			0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
148			0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
149			0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
150			0x5 0x0>;
151		rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
152			0xa60 0x40 0x10 0x0>;
153		rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
154		rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
155	};
156