1* Rockchip RK3288 Clock and Reset Unit
2
3The RK3288 clock controller generates and supplies clock to various
4controllers within the SoC and also implements a reset controller for SoC
5peripherals.
6
7Required Properties:
8
9- compatible: should be "rockchip,rk3288-cru"
10- reg: physical base address of the controller and length of memory mapped
11  region.
12- #clock-cells: should be 1.
13- #reset-cells: should be 1.
14
15Optional Properties:
16
17- rockchip,grf: phandle to the syscon managing the "general register files"
18  If missing pll rates are not changable, due to the missing pll lock status.
19
20Each clock is assigned an identifier and client nodes can use this identifier
21to specify the clock which they consume. All available clocks are defined as
22preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
23used in device tree sources. Similar macros exist for the reset sources in
24these files.
25
26External clocks:
27
28There are several clocks that are generated outside the SoC. It is expected
29that they are defined using standard clock bindings with following
30clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "xin32k" - rtc clock - optional,
33 - "ext_i2s" - external I2S clock - optional,
34 - "ext_hsadc" - external HSADC clock - optional,
35 - "ext_edp_24m" - external display port clock - optional,
36 - "ext_vip" - external VIP clock - optional,
37 - "ext_isp" - external ISP clock - optional,
38 - "ext_jtag" - external JTAG clock - optional
39
40Example: Clock controller node:
41
42	cru: cru@20000000 {
43		compatible = "rockchip,rk3188-cru";
44		reg = <0x20000000 0x1000>;
45		rockchip,grf = <&grf>;
46
47		#clock-cells = <1>;
48		#reset-cells = <1>;
49	};
50
51Example: UART controller node that consumes the clock generated by the clock
52  controller:
53
54	uart0: serial@10124000 {
55		compatible = "snps,dw-apb-uart";
56		reg = <0x10124000 0x400>;
57		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
58		reg-shift = <2>;
59		reg-io-width = <1>;
60		clocks = <&cru SCLK_UART0>;
61	};
62