xref: /openbmc/u-boot/doc/SPI/README.ti_qspi_flash (revision 2f24223ae150d9496694885cee401f4525b72acb)
1*2f24223aSPoddar, SouravQSPI U-boot support
2*2f24223aSPoddar, Sourav------------------
3*2f24223aSPoddar, Sourav
4*2f24223aSPoddar, SouravHost processor is connected to serial flash device via qpsi
5*2f24223aSPoddar, Souravinterface. QSPI is a kind of spi module that allows single,
6*2f24223aSPoddar, Souravdual and quad read access to external spi devices. The module
7*2f24223aSPoddar, Souravhas a memory mapped interface which provide direct interface
8*2f24223aSPoddar, Souravfor accessing data form external spi devices.
9*2f24223aSPoddar, Sourav
10*2f24223aSPoddar, SouravThe one QSPI in the device is primarily intended for fast booting
11*2f24223aSPoddar, Souravfrom Quad SPI flash devices.
12*2f24223aSPoddar, Sourav
13*2f24223aSPoddar, SouravUsecase
14*2f24223aSPoddar, Sourav-------
15*2f24223aSPoddar, Sourav
16*2f24223aSPoddar, SouravMLO/u-boot.img will be flashed from SD/MMC to the flash device
17*2f24223aSPoddar, Souravusing serial flash erase and write commands. Then, switch settings
18*2f24223aSPoddar, Souravwill be changed to qspi boot. Then, the ROM code will read MLO
19*2f24223aSPoddar, Souravfrom the predefined location in the flash, where it was flashed and
20*2f24223aSPoddar, Souravexecute it after storing it in SDRAM. Then, the MLO will read
21*2f24223aSPoddar, Souravu-boot.img from flash and execute it from SDRAM.
22*2f24223aSPoddar, Sourav
23*2f24223aSPoddar, SouravSPI mode
24*2f24223aSPoddar, Sourav-------
25*2f24223aSPoddar, SouravSPI mode uses mtd spi framework for transfer and reception of data.
26*2f24223aSPoddar, SouravCan be used in:
27*2f24223aSPoddar, Sourav1. Normal mode: use single pin for transfers
28*2f24223aSPoddar, Sourav2. Dual Mode: use two pins for transfers.
29*2f24223aSPoddar, Sourav3. Quad mode: use four pin for transfer
30*2f24223aSPoddar, Sourav
31*2f24223aSPoddar, SouravMemory mapped read mode
32*2f24223aSPoddar, Sourav-----------------------
33*2f24223aSPoddar, SouravIn this, SPI controller is configured using configuration port and then
34*2f24223aSPoddar, Souravcontroler is switched to memory mapped port for data read.
35*2f24223aSPoddar, Sourav
36*2f24223aSPoddar, SouravDriver
37*2f24223aSPoddar, Sourav------
38*2f24223aSPoddar, Souravdrivers/qspi/ti_qspi.c
39*2f24223aSPoddar, Sourav    - Newly created file which is responsible for configuring the
40*2f24223aSPoddar, Sourav	qspi controller and also for providing the low level api which
41*2f24223aSPoddar, Sourav	is responsible for transferring the datas from host controller
42*2f24223aSPoddar, Sourav	to flash device and vice versa.
43*2f24223aSPoddar, Sourav
44*2f24223aSPoddar, SouravTesting
45*2f24223aSPoddar, Sourav-------
46*2f24223aSPoddar, SouravA seperated file named README.dra_qspi_test has been created which gives all the
47*2f24223aSPoddar, Souravdetails about the commands required to test qspi at u-boot level.
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