1# 2# Copyright (C) 2014, Simon Glass <sjg@chromium.org> 3# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4# 5# SPDX-License-Identifier: GPL-2.0+ 6# 7 8U-Boot on x86 9============= 10 11This document describes the information about U-Boot running on x86 targets, 12including supported boards, build instructions, todo list, etc. 13 14Status 15------ 16U-Boot supports running as a coreboot [1] payload on x86. So far only Link 17(Chromebook Pixel) has been tested, but it should work with minimal adjustments 18on other x86 boards since coreboot deals with most of the low-level details. 19 20U-Boot also supports booting directly from x86 reset vector without coreboot, 21aka raw support or bare support. Currently Link, Intel Crown Bay, Intel 22Minnowboard Max and Intel Galileo support running U-Boot 'bare metal'. 23 24As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit 25Linux kernel as part of a FIT image. It also supports a compressed zImage. 26 27Build Instructions 28------------------ 29Building U-Boot as a coreboot payload is just like building U-Boot for targets 30on other architectures, like below: 31 32$ make coreboot-x86_defconfig 33$ make all 34 35Note this default configuration will build a U-Boot payload for the Link board. 36To build a coreboot payload against another board, you can change the build 37configuration during the 'make menuconfig' process. 38 39x86 architecture ---> 40 ... 41 (chromebook_link) Board configuration file 42 (chromebook_link) Board Device Tree Source (dts) file 43 (0x19200000) Board specific Cache-As-RAM (CAR) address 44 (0x4000) Board specific Cache-As-RAM (CAR) size 45 46Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' 47to point to a new board. You can also change the Cache-As-RAM (CAR) related 48settings here if the default values do not fit your new board. 49 50Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a 51little bit tricky, as generally it requires several binary blobs which are not 52shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is 53not turned on by default in the U-Boot source tree. Firstly, you need turn it 54on by enabling the ROM build: 55 56$ export BUILD_ROM=y 57 58This tells the Makefile to build u-boot.rom as a target. 59 60Link-specific instructions: 61 62First, you need the following binary blobs: 63 64* descriptor.bin - Intel flash descriptor 65* me.bin - Intel Management Engine 66* mrc.bin - Memory Reference Code, which sets up SDRAM 67* video ROM - sets up the display 68 69You can get these binary blobs by: 70 71$ git clone http://review.coreboot.org/p/blobs.git 72$ cd blobs 73 74Find the following files: 75 76* ./mainboard/google/link/descriptor.bin 77* ./mainboard/google/link/me.bin 78* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin 79 80The 3rd one should be renamed to mrc.bin. 81As for the video ROM, you can get it here [2]. 82Make sure all these binary blobs are put in the board directory. 83 84Now you can build U-Boot and obtain u-boot.rom: 85 86$ make chromebook_link_defconfig 87$ make all 88 89Intel Crown Bay specific instructions: 90 91U-Boot support of Intel Crown Bay board [3] relies on a binary blob called 92Firmware Support Package [4] to perform all the necessary initialization steps 93as documented in the BIOS Writer Guide, including initialization of the CPU, 94memory controller, chipset and certain bus interfaces. 95 96Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, 97install it on your host and locate the FSP binary blob. Note this platform 98also requires a Chipset Micro Code (CMC) state machine binary to be present in 99the SPI flash where u-boot.rom resides, and this CMC binary blob can be found 100in this FSP package too. 101 102* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd 103* ./Microcode/C0_22211.BIN 104 105Rename the first one to fsp.bin and second one to cmc.bin and put them in the 106board directory. 107 108Now you can build U-Boot and obtain u-boot.rom 109 110$ make crownbay_defconfig 111$ make all 112 113Intel Minnowboard Max instructions: 114 115This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. 116Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at 117the time of writing). Put it in the board directory: 118board/intel/minnowmax/fsp.bin 119 120Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same 121directory: board/intel/minnowmax/vga.bin 122 123You still need two more binary blobs. These come from the sample SPI image 124provided in the FSP (SPI.bin at the time of writing). 125 126Use ifdtool in the U-Boot tools directory to extract the images from that 127file, for example: 128 129 $ ./tools/ifdtool -x BayleyBay/SPI.bin 130 $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin 131 $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin 132 133Now you can build U-Boot and obtain u-boot.rom 134 135$ make minnowmax_defconfig 136$ make all 137 138Intel Galileo instructions: 139 140Only one binary blob is needed for Remote Management Unit (RMU) within Intel 141Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is 142needed by the Quark SoC itself. 143 144You can get the binary blob from Quark Board Support Package from Intel website: 145 146* ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin 147 148Rename the file and put it to the board directory by: 149 150 $ cp RMU.bin board/intel/galileo/rmu.bin 151 152Now you can build U-Boot and obtain u-boot.rom 153 154$ make galileo_defconfig 155$ make all 156 157Test with coreboot 158------------------ 159For testing U-Boot as the coreboot payload, there are things that need be paid 160attention to. coreboot supports loading an ELF executable and a 32-bit plain 161binary, as well as other supported payloads. With the default configuration, 162U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the 163generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool 164provided by coreboot) manually as coreboot's 'make menuconfig' does not provide 165this capability yet. The command is as follows: 166 167# in the coreboot root directory 168$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \ 169 -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015 170 171Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the 172symbol address of _start (in arch/x86/cpu/start.S). 173 174If you want to use ELF as the coreboot payload, change U-Boot configuration to 175use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE. 176 177To enable video you must enable these options in coreboot: 178 179 - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5)) 180 - Keep VESA framebuffer 181 182At present it seems that for Minnowboard Max, coreboot does not pass through 183the video information correctly (it always says the resolution is 0x0). This 184works correctly for link though. 185 186 187CPU Microcode 188------------- 189Modern CPUs usually require a special bit stream called microcode [5] to be 190loaded on the processor after power up in order to function properly. U-Boot 191has already integrated these as hex dumps in the source tree. 192 193Driver Model 194------------ 195x86 has been converted to use driver model for serial and GPIO. 196 197Device Tree 198----------- 199x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to 200be turned on. Not every device on the board is configured via device tree, but 201more and more devices will be added as time goes by. Check out the directory 202arch/x86/dts/ for these device tree source files. 203 204Useful Commands 205--------------- 206 207In keeping with the U-Boot philosophy of providing functions to check and 208adjust internal settings, there are several x86-specific commands that may be 209useful: 210 211hob - Display information about Firmware Support Package (FSP) Hand-off 212 Block. This is only available on platforms which use FSP, mostly 213 Atom. 214iod - Display I/O memory 215iow - Write I/O memory 216mtrr - List and set the Memory Type Range Registers (MTRR). These are used to 217 tell the CPU whether memory is cacheable and if so the cache write 218 mode to use. U-Boot sets up some reasonable values but you can 219 adjust then with this command. 220 221Development Flow 222---------------- 223These notes are for those who want to port U-Boot to a new x86 platform. 224 225Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment. 226The Dediprog em100 can be used on Linux. The em100 tool is available here: 227 228 http://review.coreboot.org/p/em100.git 229 230On Minnowboard Max the following command line can be used: 231 232 sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r 233 234A suitable clip for connecting over the SPI flash chip is here: 235 236 http://www.dediprog.com/pd/programmer-accessories/EM-TC-8 237 238This allows you to override the SPI flash contents for development purposes. 239Typically you can write to the em100 in around 1200ms, considerably faster 240than programming the real flash device each time. The only important 241limitation of the em100 is that it only supports SPI bus speeds up to 20MHz. 242This means that images must be set to boot with that speed. This is an 243Intel-specific feature - e.g. tools/ifttool has an option to set the SPI 244speed in the SPI descriptor region. 245 246If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly 247easy to fit it in. You can follow the Minnowboard Max implementation, for 248example. Hopefully you will just need to create new files similar to those 249in arch/x86/cpu/baytrail which provide Bay Trail support. 250 251If you are not using an FSP you have more freedom and more responsibility. 252The ivybridge support works this way, although it still uses a ROM for 253graphics and still has binary blobs containing Intel code. You should aim to 254support all important peripherals on your platform including video and storage. 255Use the device tree for configuration where possible. 256 257For the microcode you can create a suitable device tree file using the 258microcode tool: 259 260 ./tools/microcode-tool -d microcode.dat create <model> 261 262or if you only have header files and not the full Intel microcode.dat database: 263 264 ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \ 265 -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \ 266 create all 267 268These are written to arch/x86/dts/microcode/ by default. 269 270Note that it is possible to just add the micrcode for your CPU if you know its 271model. U-Boot prints this information when it starts 272 273 CPU: x86_64, vendor Intel, device 30673h 274 275so here we can use the M0130673322 file. 276 277If you platform can display POST codes on two little 7-segment displays on 278the board, then you can use post_code() calls from C or assembler to monitor 279boot progress. This can be good for debugging. 280 281If not, you can try to get serial working as early as possible. The early 282debug serial port may be useful here. See setup_early_uart() for an example. 283 284TODO List 285--------- 286- Audio 287- Chrome OS verified boot 288- SMI and ACPI support, to provide platform info and facilities to Linux 289 290References 291---------- 292[1] http://www.coreboot.org 293[2] http://www.coreboot.org/~stepan/pci8086,0166.rom 294[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html 295[4] http://www.intel.com/fsp 296[5] http://en.wikipedia.org/wiki/Microcode 297