1# 2# Copyright (C) 2014, Simon Glass <sjg@chromium.org> 3# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4# 5# SPDX-License-Identifier: GPL-2.0+ 6# 7 8U-Boot on x86 9============= 10 11This document describes the information about U-Boot running on x86 targets, 12including supported boards, build instructions, todo list, etc. 13 14Status 15------ 16U-Boot supports running as a coreboot [1] payload on x86. So far only Link 17(Chromebook Pixel) has been tested, but it should work with minimal adjustments 18on other x86 boards since coreboot deals with most of the low-level details. 19 20U-Boot also supports booting directly from x86 reset vector without coreboot, 21aka raw support or bare support. Currently Link, Intel Crown Bay and Intel 22Minnowboard Max support running U-Boot 'bare metal'. 23 24As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit 25Linux kernel as part of a FIT image. It also supports a compressed zImage. 26 27Build Instructions 28------------------ 29Building U-Boot as a coreboot payload is just like building U-Boot for targets 30on other architectures, like below: 31 32$ make coreboot-x86_defconfig 33$ make all 34 35Note this default configuration will build a U-Boot payload for the Link board. 36To build a coreboot payload against another board, you can change the build 37configuration during the 'make menuconfig' process. 38 39x86 architecture ---> 40 ... 41 (chromebook_link) Board configuration file 42 (chromebook_link) Board Device Tree Source (dts) file 43 (0x19200000) Board specific Cache-As-RAM (CAR) address 44 (0x4000) Board specific Cache-As-RAM (CAR) size 45 46Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' 47to point to a new board. You can also change the Cache-As-RAM (CAR) related 48settings here if the default values do not fit your new board. 49 50Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a 51little bit tricky, as generally it requires several binary blobs which are not 52shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is 53not turned on by default in the U-Boot source tree. Firstly, you need turn it 54on by enabling the ROM build: 55 56$ export BUILD_ROM=y 57 58This tells the Makefile to build u-boot.rom as a target. 59 60Link-specific instructions: 61 62First, you need the following binary blobs: 63 64* descriptor.bin - Intel flash descriptor 65* me.bin - Intel Management Engine 66* mrc.bin - Memory Reference Code, which sets up SDRAM 67* video ROM - sets up the display 68 69You can get these binary blobs by: 70 71$ git clone http://review.coreboot.org/p/blobs.git 72$ cd blobs 73 74Find the following files: 75 76* ./mainboard/google/link/descriptor.bin 77* ./mainboard/google/link/me.bin 78* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin 79 80The 3rd one should be renamed to mrc.bin. 81As for the video ROM, you can get it here [2]. 82Make sure all these binary blobs are put in the board directory. 83 84Now you can build U-Boot and obtain u-boot.rom: 85 86$ make chromebook_link_defconfig 87$ make all 88 89Intel Crown Bay specific instructions: 90 91U-Boot support of Intel Crown Bay board [3] relies on a binary blob called 92Firmware Support Package [4] to perform all the necessary initialization steps 93as documented in the BIOS Writer Guide, including initialization of the CPU, 94memory controller, chipset and certain bus interfaces. 95 96Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, 97install it on your host and locate the FSP binary blob. Note this platform 98also requires a Chipset Micro Code (CMC) state machine binary to be present in 99the SPI flash where u-boot.rom resides, and this CMC binary blob can be found 100in this FSP package too. 101 102* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd 103* ./Microcode/C0_22211.BIN 104 105Rename the first one to fsp.bin and second one to cmc.bin and put them in the 106board directory. 107 108Now you can build U-Boot and obtain u-boot.rom 109 110$ make crownbay_defconfig 111$ make all 112 113 114Intel Minnowboard Max instructions: 115 116This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. 117Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at 118the time of writing). Put it in the board directory: 119board/intel/minnowmax/fsp.bin 120 121Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same 122directory: board/intel/minnowmax/vga.bin 123 124You still need two more binary blobs. These come from the sample SPI image 125provided in the FSP (SPI.bin at the time of writing). 126 127Use ifdtool in the U-Boot tools directory to extract the images from that 128file, for example: 129 130 $ ./tools/ifdtool -x BayleyBay/SPI.bin 131 $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin 132 $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin 133 134Now you can build U-Boot and obtain u-boot.rom 135 136$ make minnowmax_defconfig 137$ make all 138 139 140Test with coreboot 141------------------ 142For testing U-Boot as the coreboot payload, there are things that need be paid 143attention to. coreboot supports loading an ELF executable and a 32-bit plain 144binary, as well as other supported payloads. With the default configuration, 145U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the 146generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool 147provided by coreboot) manually as coreboot's 'make menuconfig' does not provide 148this capability yet. The command is as follows: 149 150# in the coreboot root directory 151$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \ 152 -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015 153 154Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the 155symbol address of _start (in arch/x86/cpu/start.S). 156 157If you want to use ELF as the coreboot payload, change U-Boot configuration to 158use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE. 159 160To enable video you must enable these options in coreboot: 161 162 - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5)) 163 - Keep VESA framebuffer 164 165At present it seems that for Minnowboard Max, coreboot does not pass through 166the video information correctly (it always says the resolution is 0x0). This 167works correctly for link though. 168 169 170CPU Microcode 171------------- 172Modern CPUs usually require a special bit stream called microcode [5] to be 173loaded on the processor after power up in order to function properly. U-Boot 174has already integrated these as hex dumps in the source tree. 175 176Driver Model 177------------ 178x86 has been converted to use driver model for serial and GPIO. 179 180Device Tree 181----------- 182x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to 183be turned on. Not every device on the board is configured via device tree, but 184more and more devices will be added as time goes by. Check out the directory 185arch/x86/dts/ for these device tree source files. 186 187Useful Commands 188--------------- 189 190In keeping with the U-Boot philosophy of providing functions to check and 191adjust internal settings, there are several x86-specific commands that may be 192useful: 193 194hob - Display information about Firmware Support Package (FSP) Hand-off 195 Block. This is only available on platforms which use FSP, mostly 196 Atom. 197iod - Display I/O memory 198iow - Write I/O memory 199mtrr - List and set the Memory Type Range Registers (MTRR). These are used to 200 tell the CPU whether memory is cacheable and if so the cache write 201 mode to use. U-Boot sets up some reasonable values but you can 202 adjust then with this command. 203 204Development Flow 205---------------- 206 207These notes are for those who want to port U-Boot to a new x86 platform. 208 209Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment. 210The Dediprog em100 can be used on Linux. The em100 tool is available here: 211 212 http://review.coreboot.org/p/em100.git 213 214On Minnowboard Max the following command line can be used: 215 216 sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r 217 218A suitable clip for connecting over the SPI flash chip is here: 219 220 http://www.dediprog.com/pd/programmer-accessories/EM-TC-8 221 222This allows you to override the SPI flash contents for development purposes. 223Typically you can write to the em100 in around 1200ms, considerably faster 224than programming the real flash device each time. The only important 225limitation of the em100 is that it only supports SPI bus speeds up to 20MHz. 226This means that images must be set to boot with that speed. This is an 227Intel-specific feature - e.g. tools/ifttool has an option to set the SPI 228speed in the SPI descriptor region. 229 230If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly 231easy to fit it in. You can follow the Minnowboard Max implementation, for 232example. Hopefully you will just need to create new files similar to those 233in arch/x86/cpu/baytrail which provide Bay Trail support. 234 235If you are not using an FSP you have more freedom and more responsibility. 236The ivybridge support works this way, although it still uses a ROM for 237graphics and still has binary blobs containing Intel code. You should aim to 238support all important peripherals on your platform including video and storage. 239Use the device tree for configuration where possible. 240 241For the microcode you can create a suitable device tree file using the 242microcode tool: 243 244 ./tools/microcode-tool -d microcode.dat create <model> 245 246or if you only have header files and not the full Intel microcode.dat database: 247 248 ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \ 249 -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \ 250 create all 251 252These are written to arch/x86/dts/microcode/ by default. 253 254Note that it is possible to just add the micrcode for your CPU if you know its 255model. U-Boot prints this information when it starts 256 257 CPU: x86_64, vendor Intel, device 30673h 258 259so here we can use the M0130673322 file. 260 261If you platform can display POST codes on two little 7-segment displays on 262the board, then you can use post_code() calls from C or assembler to monitor 263boot progress. This can be good for debugging. 264 265If not, you can try to get serial working as early as possible. The early 266debug serial port may be useful here. See setup_early_uart() for an example. 267 268TODO List 269--------- 270- Audio 271- Chrome OS verified boot 272- SMI and ACPI support, to provide platform info and facilities to Linux 273 274References 275---------- 276[1] http://www.coreboot.org 277[2] http://www.coreboot.org/~stepan/pci8086,0166.rom 278[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html 279[4] http://www.intel.com/fsp 280[5] http://en.wikipedia.org/wiki/Microcode 281