1# 2# Copyright (C) 2014, Simon Glass <sjg@chromium.org> 3# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4# 5# SPDX-License-Identifier: GPL-2.0+ 6# 7 8U-Boot on x86 9============= 10 11This document describes the information about U-Boot running on x86 targets, 12including supported boards, build instructions, todo list, etc. 13 14Status 15------ 16U-Boot supports running as a coreboot [1] payload on x86. So far only Link 17(Chromebook Pixel) has been tested, but it should work with minimal adjustments 18on other x86 boards since coreboot deals with most of the low-level details. 19 20U-Boot also supports booting directly from x86 reset vector without coreboot, 21aka raw support or bare support. Currently Link and Intel Crown Bay board 22support running U-Boot 'bare metal'. 23 24As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux 25kernel as part of a FIT image. It also supports a compressed zImage. 26 27Build Instructions 28------------------ 29Building U-Boot as a coreboot payload is just like building U-Boot for targets 30on other architectures, like below: 31 32$ make coreboot-x86_defconfig 33$ make all 34 35Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a 36little bit tricky, as generally it requires several binary blobs which are not 37shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is 38not turned on by default in the U-Boot source tree. Firstly, you need turn it 39on by uncommenting the following line in the main U-Boot Makefile: 40 41# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom 42 43Link-specific instructions: 44 45First, you need the following binary blobs: 46 47* descriptor.bin - Intel flash descriptor 48* me.bin - Intel Management Engine 49* mrc.bin - Memory Reference Code, which sets up SDRAM 50* video ROM - sets up the display 51 52You can get these binary blobs by: 53 54$ git clone http://review.coreboot.org/p/blobs.git 55$ cd blobs 56 57Find the following files: 58 59* ./mainboard/google/link/descriptor.bin 60* ./mainboard/google/link/me.bin 61* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin 62 63The 3rd one should be renamed to mrc.bin. 64As for the video ROM, you can get it here [2]. 65Make sure all these binary blobs are put in the board directory. 66 67Now you can build U-Boot and obtain u-boot.rom: 68 69$ make chromebook_link_defconfig 70$ make all 71 72Intel Crown Bay specific instructions: 73 74U-Boot support of Intel Crown Bay board [3] relies on a binary blob called 75Firmware Support Package [4] to perform all the necessary initialization steps 76as documented in the BIOS Writer Guide, including initialization of the CPU, 77memory controller, chipset and certain bus interfaces. 78 79Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, 80install it on your host and locate the FSP binary blob. Note this platform 81also requires a Chipset Micro Code (CMC) state machine binary to be present in 82the SPI flash where u-boot.rom resides, and this CMC binary blob can be found 83in this FSP package too. 84 85* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd 86* ./Microcode/C0_22211.BIN 87 88Rename the first one to fsp.bin and second one to cmc.bin and put them in the 89board directory. 90 91Now you can build U-Boot and obtaim u-boot.rom 92 93$ make crownbay_defconfig 94$ make all 95 96CPU Microcode 97------------- 98Modern CPU usually requires a special bit stream called microcode [5] to be 99loaded on the processor after power up in order to function properly. U-Boot 100has already integrated these as hex dumps in the source tree. 101 102Driver Model 103------------ 104x86 has been converted to use driver model for serial and GPIO. 105 106Device Tree 107----------- 108x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to 109be turned on. Not every device on the board is configured via devie tree, but 110more and more devices will be added as time goes by. Check out the directory 111arch/x86/dts/ for these device tree source files. 112 113TODO List 114--------- 115- MTRR support (for performance) 116- Audio 117- Chrome OS verified boot 118- SMI and ACPI support, to provide platform info and facilities to Linux 119 120References 121---------- 122[1] http://www.coreboot.org 123[2] http://www.coreboot.org/~stepan/pci8086,0166.rom 124[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html 125[4] http://www.intel.com/fsp 126[5] http://en.wikipedia.org/wiki/Microcode 127