1# 2# Copyright (C) 2014, Simon Glass <sjg@chromium.org> 3# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4# 5# SPDX-License-Identifier: GPL-2.0+ 6# 7 8U-Boot on x86 9============= 10 11This document describes the information about U-Boot running on x86 targets, 12including supported boards, build instructions, todo list, etc. 13 14Status 15------ 16U-Boot supports running as a coreboot [1] payload on x86. So far only Link 17(Chromebook Pixel) and QEMU [2] x86 targets have been tested, but it should 18work with minimal adjustments on other x86 boards since coreboot deals with 19most of the low-level details. 20 21U-Boot also supports booting directly from x86 reset vector without coreboot, 22aka raw support or bare support. Currently Link, QEMU x86 targets and all 23Intel boards support running U-Boot 'bare metal'. 24 25As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit 26Linux kernel as part of a FIT image. It also supports a compressed zImage. 27 28Build Instructions 29------------------ 30Building U-Boot as a coreboot payload is just like building U-Boot for targets 31on other architectures, like below: 32 33$ make coreboot-x86_defconfig 34$ make all 35 36Note this default configuration will build a U-Boot payload for the QEMU board. 37To build a coreboot payload against another board, you can change the build 38configuration during the 'make menuconfig' process. 39 40x86 architecture ---> 41 ... 42 (qemu-x86) Board configuration file 43 (qemu-x86_i440fx) Board Device Tree Source (dts) file 44 (0x01920000) Board specific Cache-As-RAM (CAR) address 45 (0x4000) Board specific Cache-As-RAM (CAR) size 46 47Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' 48to point to a new board. You can also change the Cache-As-RAM (CAR) related 49settings here if the default values do not fit your new board. 50 51Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a 52little bit tricky, as generally it requires several binary blobs which are not 53shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is 54not turned on by default in the U-Boot source tree. Firstly, you need turn it 55on by enabling the ROM build: 56 57$ export BUILD_ROM=y 58 59This tells the Makefile to build u-boot.rom as a target. 60 61Link-specific instructions: 62 63First, you need the following binary blobs: 64 65* descriptor.bin - Intel flash descriptor 66* me.bin - Intel Management Engine 67* mrc.bin - Memory Reference Code, which sets up SDRAM 68* video ROM - sets up the display 69 70You can get these binary blobs by: 71 72$ git clone http://review.coreboot.org/p/blobs.git 73$ cd blobs 74 75Find the following files: 76 77* ./mainboard/google/link/descriptor.bin 78* ./mainboard/google/link/me.bin 79* ./northbridge/intel/sandybridge/systemagent-r6.bin 80 81The 3rd one should be renamed to mrc.bin. 82As for the video ROM, you can get it here [3] and rename it to vga.bin. 83Make sure all these binary blobs are put in the board directory. 84 85Now you can build U-Boot and obtain u-boot.rom: 86 87$ make chromebook_link_defconfig 88$ make all 89 90Intel Crown Bay specific instructions: 91 92U-Boot support of Intel Crown Bay board [4] relies on a binary blob called 93Firmware Support Package [5] to perform all the necessary initialization steps 94as documented in the BIOS Writer Guide, including initialization of the CPU, 95memory controller, chipset and certain bus interfaces. 96 97Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, 98install it on your host and locate the FSP binary blob. Note this platform 99also requires a Chipset Micro Code (CMC) state machine binary to be present in 100the SPI flash where u-boot.rom resides, and this CMC binary blob can be found 101in this FSP package too. 102 103* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd 104* ./Microcode/C0_22211.BIN 105 106Rename the first one to fsp.bin and second one to cmc.bin and put them in the 107board directory. 108 109Note the FSP release version 001 has a bug which could cause random endless 110loop during the FspInit call. This bug was published by Intel although Intel 111did not describe any details. We need manually apply the patch to the FSP 112binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP 113binary, change the following five bytes values from orginally E8 42 FF FF FF 114to B8 00 80 0B 00. 115 116As for the video ROM, you need manually extract it from the Intel provided 117BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM 118ID 8086:4108, extract and save it as vga.bin in the board directory. 119 120Now you can build U-Boot and obtain u-boot.rom 121 122$ make crownbay_defconfig 123$ make all 124 125Intel Minnowboard Max instructions: 126 127This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. 128Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at 129the time of writing). Put it in the board directory: 130board/intel/minnowmax/fsp.bin 131 132Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same 133directory: board/intel/minnowmax/vga.bin 134 135You still need two more binary blobs. The first comes from the original 136firmware image available from: 137 138http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip 139 140Unzip it: 141 142 $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip 143 144Use ifdtool in the U-Boot tools directory to extract the images from that 145file, for example: 146 147 $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin 148 149This will provide the descriptor file - copy this into the correct place: 150 151 $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin 152 153Then do the same with the sample SPI image provided in the FSP (SPI.bin at 154the time of writing) to obtain the last image. Note that this will also 155produce a flash descriptor file, but it does not seem to work, probably 156because it is not designed for the Minnowmax. That is why you need to get 157the flash descriptor from the original firmware as above. 158 159 $ ./tools/ifdtool -x BayleyBay/SPI.bin 160 $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin 161 162Now you can build U-Boot and obtain u-boot.rom 163 164$ make minnowmax_defconfig 165$ make all 166 167Intel Galileo instructions: 168 169Only one binary blob is needed for Remote Management Unit (RMU) within Intel 170Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is 171needed by the Quark SoC itself. 172 173You can get the binary blob from Quark Board Support Package from Intel website: 174 175* ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin 176 177Rename the file and put it to the board directory by: 178 179 $ cp RMU.bin board/intel/galileo/rmu.bin 180 181Now you can build U-Boot and obtain u-boot.rom 182 183$ make galileo_defconfig 184$ make all 185 186QEMU x86 target instructions: 187 188To build u-boot.rom for QEMU x86 targets, just simply run 189 190$ make qemu-x86_defconfig 191$ make all 192 193Note this default configuration will build a U-Boot for the QEMU x86 i440FX 194board. To build a U-Boot against QEMU x86 Q35 board, you can change the build 195configuration during the 'make menuconfig' process like below: 196 197Device Tree Control ---> 198 ... 199 (qemu-x86_q35) Default Device Tree for DT control 200 201Test with coreboot 202------------------ 203For testing U-Boot as the coreboot payload, there are things that need be paid 204attention to. coreboot supports loading an ELF executable and a 32-bit plain 205binary, as well as other supported payloads. With the default configuration, 206U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the 207generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool 208provided by coreboot) manually as coreboot's 'make menuconfig' does not provide 209this capability yet. The command is as follows: 210 211# in the coreboot root directory 212$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \ 213 -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015 214 215Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the 216symbol address of _start (in arch/x86/cpu/start.S). 217 218If you want to use ELF as the coreboot payload, change U-Boot configuration to 219use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE. 220 221To enable video you must enable these options in coreboot: 222 223 - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5)) 224 - Keep VESA framebuffer 225 226At present it seems that for Minnowboard Max, coreboot does not pass through 227the video information correctly (it always says the resolution is 0x0). This 228works correctly for link though. 229 230Test with QEMU 231-------------- 232QEMU is a fancy emulator that can enable us to test U-Boot without access to 233a real x86 board. Please make sure your QEMU version is 2.3.0 or above test 234U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows: 235 236$ qemu-system-i386 -nographic -bios path/to/u-boot.rom 237 238This will instantiate an emulated x86 board with i440FX and PIIX chipset. QEMU 239also supports emulating an x86 board with Q35 and ICH9 based chipset, which is 240also supported by U-Boot. To instantiate such a machine, call QEMU with: 241 242$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -M q35 243 244Note by default QEMU instantiated boards only have 128 MiB system memory. But 245it is enough to have U-Boot boot and function correctly. You can increase the 246system memory by pass '-m' parameter to QEMU if you want more memory: 247 248$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 249 250This creates a board with 1 GiB system memory. Currently U-Boot for QEMU only 251supports 3 GiB maximum system memory and reserves the last 1 GiB address space 252for PCI device memory-mapped I/O and other stuff, so the maximum value of '-m' 253would be 3072. 254 255QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will 256show QEMU's VGA console window. Note this will disable QEMU's serial output. 257If you want to check both consoles, use '-serial stdio'. 258 259CPU Microcode 260------------- 261Modern CPUs usually require a special bit stream called microcode [8] to be 262loaded on the processor after power up in order to function properly. U-Boot 263has already integrated these as hex dumps in the source tree. 264 265SMP Support 266----------- 267On a multicore system, U-Boot is executed on the bootstrap processor (BSP). 268Additional application processors (AP) can be brought up by U-Boot. In order to 269have an SMP kernel to discover all of the available processors, U-Boot needs to 270prepare configuration tables which contain the multi-CPUs information before 271loading the OS kernel. Currently U-Boot supports generating two types of tables 272for SMP, called Simple Firmware Interface (SFI) [9] and Multi-Processor (MP) 273[10] tables. The writing of these two tables are controlled by two Kconfig 274options GENERATE_SFI_TABLE and GENERATE_MP_TABLE. 275 276Driver Model 277------------ 278x86 has been converted to use driver model for serial and GPIO. 279 280Device Tree 281----------- 282x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to 283be turned on. Not every device on the board is configured via device tree, but 284more and more devices will be added as time goes by. Check out the directory 285arch/x86/dts/ for these device tree source files. 286 287Useful Commands 288--------------- 289In keeping with the U-Boot philosophy of providing functions to check and 290adjust internal settings, there are several x86-specific commands that may be 291useful: 292 293hob - Display information about Firmware Support Package (FSP) Hand-off 294 Block. This is only available on platforms which use FSP, mostly 295 Atom. 296iod - Display I/O memory 297iow - Write I/O memory 298mtrr - List and set the Memory Type Range Registers (MTRR). These are used to 299 tell the CPU whether memory is cacheable and if so the cache write 300 mode to use. U-Boot sets up some reasonable values but you can 301 adjust then with this command. 302 303Development Flow 304---------------- 305These notes are for those who want to port U-Boot to a new x86 platform. 306 307Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment. 308The Dediprog em100 can be used on Linux. The em100 tool is available here: 309 310 http://review.coreboot.org/p/em100.git 311 312On Minnowboard Max the following command line can be used: 313 314 sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r 315 316A suitable clip for connecting over the SPI flash chip is here: 317 318 http://www.dediprog.com/pd/programmer-accessories/EM-TC-8 319 320This allows you to override the SPI flash contents for development purposes. 321Typically you can write to the em100 in around 1200ms, considerably faster 322than programming the real flash device each time. The only important 323limitation of the em100 is that it only supports SPI bus speeds up to 20MHz. 324This means that images must be set to boot with that speed. This is an 325Intel-specific feature - e.g. tools/ifttool has an option to set the SPI 326speed in the SPI descriptor region. 327 328If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly 329easy to fit it in. You can follow the Minnowboard Max implementation, for 330example. Hopefully you will just need to create new files similar to those 331in arch/x86/cpu/baytrail which provide Bay Trail support. 332 333If you are not using an FSP you have more freedom and more responsibility. 334The ivybridge support works this way, although it still uses a ROM for 335graphics and still has binary blobs containing Intel code. You should aim to 336support all important peripherals on your platform including video and storage. 337Use the device tree for configuration where possible. 338 339For the microcode you can create a suitable device tree file using the 340microcode tool: 341 342 ./tools/microcode-tool -d microcode.dat create <model> 343 344or if you only have header files and not the full Intel microcode.dat database: 345 346 ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \ 347 -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \ 348 create all 349 350These are written to arch/x86/dts/microcode/ by default. 351 352Note that it is possible to just add the micrcode for your CPU if you know its 353model. U-Boot prints this information when it starts 354 355 CPU: x86_64, vendor Intel, device 30673h 356 357so here we can use the M0130673322 file. 358 359If you platform can display POST codes on two little 7-segment displays on 360the board, then you can use post_code() calls from C or assembler to monitor 361boot progress. This can be good for debugging. 362 363If not, you can try to get serial working as early as possible. The early 364debug serial port may be useful here. See setup_early_uart() for an example. 365 366TODO List 367--------- 368- Audio 369- Chrome OS verified boot 370- SMI and ACPI support, to provide platform info and facilities to Linux 371 372References 373---------- 374[1] http://www.coreboot.org 375[2] http://www.qemu.org 376[3] http://www.coreboot.org/~stepan/pci8086,0166.rom 377[4] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html 378[5] http://www.intel.com/fsp 379[6] http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html 380[7] http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/ 381[8] http://en.wikipedia.org/wiki/Microcode 382[9] http://simplefirmware.org 383[10] http://www.intel.com/design/archives/processors/pro/docs/242016.htm 384