1# 2# Copyright (C) 2014, Simon Glass <sjg@chromium.org> 3# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4# 5# SPDX-License-Identifier: GPL-2.0+ 6# 7 8U-Boot on x86 9============= 10 11This document describes the information about U-Boot running on x86 targets, 12including supported boards, build instructions, todo list, etc. 13 14Status 15------ 16U-Boot supports running as a coreboot [1] payload on x86. So far only Link 17(Chromebook Pixel) has been tested, but it should work with minimal adjustments 18on other x86 boards since coreboot deals with most of the low-level details. 19 20U-Boot also supports booting directly from x86 reset vector without coreboot, 21aka raw support or bare support. Currently Link and Intel Crown Bay board 22support running U-Boot 'bare metal'. 23 24As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux 25kernel as part of a FIT image. It also supports a compressed zImage. 26 27Build Instructions 28------------------ 29Building U-Boot as a coreboot payload is just like building U-Boot for targets 30on other architectures, like below: 31 32$ make coreboot-x86_defconfig 33$ make all 34 35Note this default configuration will build a U-Boot payload for the Link board. 36To build a coreboot payload against another board, you can change the build 37configuration during the 'make menuconfig' process. 38 39x86 architecture ---> 40 ... 41 (chromebook_link) Board configuration file 42 (chromebook_link) Board Device Tree Source (dts) file 43 (0x19200000) Board specific Cache-As-RAM (CAR) address 44 (0x4000) Board specific Cache-As-RAM (CAR) size 45 46Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' 47to point to a new board. You can also change the Cache-As-RAM (CAR) related 48settings here if the default values do not fit your new board. 49 50Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a 51little bit tricky, as generally it requires several binary blobs which are not 52shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is 53not turned on by default in the U-Boot source tree. Firstly, you need turn it 54on by enabling the ROM build: 55 56$ export BUILD_ROM=y 57 58This tells the Makefile to build u-boot.rom as a target. 59 60Link-specific instructions: 61 62First, you need the following binary blobs: 63 64* descriptor.bin - Intel flash descriptor 65* me.bin - Intel Management Engine 66* mrc.bin - Memory Reference Code, which sets up SDRAM 67* video ROM - sets up the display 68 69You can get these binary blobs by: 70 71$ git clone http://review.coreboot.org/p/blobs.git 72$ cd blobs 73 74Find the following files: 75 76* ./mainboard/google/link/descriptor.bin 77* ./mainboard/google/link/me.bin 78* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin 79 80The 3rd one should be renamed to mrc.bin. 81As for the video ROM, you can get it here [2]. 82Make sure all these binary blobs are put in the board directory. 83 84Now you can build U-Boot and obtain u-boot.rom: 85 86$ make chromebook_link_defconfig 87$ make all 88 89Intel Crown Bay specific instructions: 90 91U-Boot support of Intel Crown Bay board [3] relies on a binary blob called 92Firmware Support Package [4] to perform all the necessary initialization steps 93as documented in the BIOS Writer Guide, including initialization of the CPU, 94memory controller, chipset and certain bus interfaces. 95 96Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, 97install it on your host and locate the FSP binary blob. Note this platform 98also requires a Chipset Micro Code (CMC) state machine binary to be present in 99the SPI flash where u-boot.rom resides, and this CMC binary blob can be found 100in this FSP package too. 101 102* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd 103* ./Microcode/C0_22211.BIN 104 105Rename the first one to fsp.bin and second one to cmc.bin and put them in the 106board directory. 107 108Now you can build U-Boot and obtain u-boot.rom 109 110$ make crownbay_defconfig 111$ make all 112 113Test with coreboot 114------------------ 115For testing U-Boot as the coreboot payload, there are things that need be paid 116attention to. coreboot supports loading an ELF executable and a 32-bit plain 117binary, as well as other supported payloads. With the default configuration, 118U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the 119generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool 120provided by coreboot) manually as coreboot's 'make menuconfig' does not provide 121this capability yet. The command is as follows: 122 123# in the coreboot root directory 124$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \ 125 -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015 126 127Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the 128symbol address of _start (in arch/x86/cpu/start.S). 129 130If you want to use ELF as the coreboot payload, change U-Boot configuration to 131use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE. 132 133CPU Microcode 134------------- 135Modern CPUs usually require a special bit stream called microcode [5] to be 136loaded on the processor after power up in order to function properly. U-Boot 137has already integrated these as hex dumps in the source tree. 138 139Driver Model 140------------ 141x86 has been converted to use driver model for serial and GPIO. 142 143Device Tree 144----------- 145x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to 146be turned on. Not every device on the board is configured via device tree, but 147more and more devices will be added as time goes by. Check out the directory 148arch/x86/dts/ for these device tree source files. 149 150Useful Commands 151--------------- 152 153In keeping with the U-Boot philosophy of providing functions to check and 154adjust internal settings, there are several x86-specific commands that may be 155useful: 156 157hob - Display information about Firmware Support Package (FSP) Hand-off 158 Block. This is only available on platforms which use FSP, mostly 159 Atom. 160iod - Display I/O memory 161iow - Write I/O memory 162mtrr - List and set the Memory Type Range Registers (MTRR). These are used to 163 tell the CPU whether memory is cacheable and if so the cache write 164 mode to use. U-Boot sets up some reasonable values but you can 165 adjust then with this command. 166 167TODO List 168--------- 169- Audio 170- Chrome OS verified boot 171- SMI and ACPI support, to provide platform info and facilities to Linux 172 173References 174---------- 175[1] http://www.coreboot.org 176[2] http://www.coreboot.org/~stepan/pci8086,0166.rom 177[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html 178[4] http://www.intel.com/fsp 179[5] http://en.wikipedia.org/wiki/Microcode 180