1U-Boot for UniPhier SoC family 2============================== 3 4 5Recommended toolchains 6---------------------- 7 8The UniPhier platform is well tested with Linaro toolchains. 9You can download pre-built toolchains from: 10 11 http://www.linaro.org/downloads/ 12 13 14Compile the source 15------------------ 16 17The source can be configured and built with the following commands: 18 19 $ make <defconfig> 20 $ make CROSS_COMPILE=<toolchain-prefix> DEVICE_TREE=<device-tree> 21 22The recommended <toolchain-prefix> is `arm-linux-gnueabihf-` for 32bit SoCs, 23`aarch64-linux-gnu-` for 64bit SoCs, but you may wish to change it to use your 24favorite compiler. 25 26The following tables show <defconfig> and <device-tree> for each board. 27 2832bit SoC boards: 29 30 Board | <defconfig> | <device-tree> 31---------------|------------------------------|------------------------------ 32LD4 reference | uniphier_ld4_sld8_defconfig | uniphier-ld4-ref (default) 33sld8 reference | uniphier_ld4_sld8_defconfig | uniphier-sld8-def 34Pro4 reference | uniphier_pro4_defconfig | uniphier-pro4-ref (default) 35Pro4 Ace | uniphier_pro4_defconfig | uniphier-pro4-ace 36Pro4 Sanji | uniphier_pro4_defconfig | uniphier-pro4-sanji 37Pro5 4KBOX | uniphier_pxs2_ld6b_defconfig | uniphier-pro5-4kbox 38PXs2 Gentil | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-gentil 39PXs2 Vodka | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-vodka (default) 40LD6b reference | uniphier_pxs2_ld6b_defconfig | uniphier-ld6b-ref 41 4264bit SoC boards: 43 44 Board | <defconfig> | <device-tree> 45---------------|-----------------------|---------------------------- 46LD11 reference | uniphier_v8_defconfig | uniphier-ld11-ref 47LD11 Global | uniphier_v8_defconfig | uniphier-ld11-global 48LD20 reference | uniphier_v8_defconfig | uniphier-ld20-ref (default) 49LD20 Global | uniphier_v8_defconfig | uniphier-ld20-global 50 51For example, to compile the source for PXs2 Vodka board, run the following: 52 53 $ make uniphier_pxs2_ld6b_defconfig 54 $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-vodka 55 56The device tree marked as (default) can be omitted. `uniphier-pxs2-vodka` is 57the default device tree for the configuration `uniphier_pxs2_ld6b_defconfig`, 58so the following gives the same result. 59 60 $ make uniphier_pxs2_ld6b_defconfig 61 $ make CROSS_COMPILE=arm-linux-gnueabihf- 62 63 64Booting 32bit SoC boards 65------------------------ 66 67The build command will generate the following: 68- u-boot.bin 69- spl/u-boot.bin 70 71U-Boot can boot UniPhier 32bit SoC boards by itself. Flash the generated images 72to the storage device (NAND or eMMC) on your board. 73 74 - spl/u-boot-spl.bin at the offset address 0x00000000 75 - u-boot.bin at the offset address 0x00020000 76 77The `u-boot-with-spl.bin` is the concatenation of the two (with appropriate 78padding), so you can also do: 79 80 - u-boot-with-spl.bin at the offset address 0x00000000 81 82If a TFTP server is available, the images can be easily updated. 83Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory, 84and run the following command at the U-Boot command line: 85 86To update the images in NAND: 87 88 => run nandupdate 89 90To update the images in eMMC: 91 92 => run emmcupdate 93 94 95Booting 64bit SoC boards 96------------------------ 97 98The build command will generate the following: 99- u-boot.bin 100 101However, U-Boot is not the first stage loader for UniPhier 64bit SoC boards. 102U-Boot serves as a non-secure boot loader loaded by [ARM Trusted Firmware], 103so you need to provide the `u-boot.bin` to the build command of ARM Trusted 104Firmware. 105 106[ARM Trusted Firmware]: https://github.com/ARM-software/arm-trusted-firmware 107 108 109UniPhier specific commands 110-------------------------- 111 112 - pinmon (enabled by CONFIG_CMD_PINMON) 113 shows the boot mode pins that has been latched at the power-on reset 114 115 - ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP) 116 shows the DDR PHY parameters set by the PHY training 117 118 - ddrmphy (enabled by CONFIG_CMD_DDRMPHY_DUMP) 119 shows the DDR Multi PHY parameters set by the PHY training 120 121 122Supported devices 123----------------- 124 125 - UART (on-chip) 126 - NAND 127 - SD/eMMC 128 - USB 2.0 (EHCI) 129 - USB 3.0 (xHCI) 130 - GPIO 131 - LAN (on-board SMSC9118) 132 - I2C 133 - EEPROM (connected to the on-board I2C bus) 134 - Support card (SRAM, NOR flash, some peripherals) 135 136 137Micro Support Card 138------------------ 139 140The recommended bit switch settings are as follows: 141 142 SW2 OFF(1)/ON(0) Description 143 ------------------------------------------ 144 bit 1 <---- BKSZ[0] 145 bit 2 ----> BKSZ[1] 146 bit 3 <---- SoC Bus Width 16/32 147 bit 4 <---- SERIAL_SEL[0] 148 bit 5 ----> SERIAL_SEL[1] 149 bit 6 ----> BOOTSWAP_EN 150 bit 7 <---- CS1/CS5 151 bit 8 <---- SOC_SERIAL_DISABLE 152 153 SW8 OFF(1)/ON(0) Description 154 ------------------------------------------ 155 bit 1 <---- CS1_SPLIT 156 bit 2 <---- CASE9_ON 157 bit 3 <---- CASE10_ON 158 bit 4 Don't Care Reserve 159 bit 5 Don't Care Reserve 160 bit 6 Don't Care Reserve 161 bit 7 ----> BURST_EN 162 bit 8 ----> FLASHBUS32_16 163 164The BKSZ[1:0] specifies the address range of memory slot and peripherals 165as follows: 166 167 BKSZ Description RAM slot Peripherals 168 -------------------------------------------------------------------- 169 0b00 15MB RAM / 1MB Peri 00000000-00efffff 00f00000-00ffffff 170 0b01 31MB RAM / 1MB Peri 00000000-01efffff 01f00000-01ffffff 171 0b10 64MB RAM / 1MB Peri 00000000-03efffff 03f00000-03ffffff 172 0b11 127MB RAM / 1MB Peri 00000000-07efffff 07f00000-07ffffff 173 174Set BSKZ[1:0] to 0b01 for U-Boot. 175This mode is the most handy because EA[24] is always supported by the save pin 176mode of the system bus. On the other hand, EA[25] is not supported for some 177newer SoCs. Even if it is, EA[25] is not connected on most of the boards. 178 179-- 180Masahiro Yamada <yamada.masahiro@socionext.com> 181Jul. 2017 182