1*c5c1af21SChin Liang See 2*c5c1af21SChin Liang See-------------------------------------------- 3*c5c1af21SChin Liang SeeSOCFPGA Documentation for U-Boot and SPL 4*c5c1af21SChin Liang See-------------------------------------------- 5*c5c1af21SChin Liang See 6*c5c1af21SChin Liang SeeThis README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore 7*c5c1af21SChin Liang Seebased SOCFPGA. To know more about the hardware itself, please refer to 8*c5c1af21SChin Liang Seewww.altera.com. 9*c5c1af21SChin Liang See 10*c5c1af21SChin Liang See 11*c5c1af21SChin Liang See-------------------------------------------- 12*c5c1af21SChin Liang Seesocfpga_dw_mmc 13*c5c1af21SChin Liang See-------------------------------------------- 14*c5c1af21SChin Liang SeeHere are macro and detailed configuration required to enable DesignWare SDMMC 15*c5c1af21SChin Liang Seecontroller support within SOCFPGA 16*c5c1af21SChin Liang See 17*c5c1af21SChin Liang See#define CONFIG_MMC 18*c5c1af21SChin Liang See-> To enable the SD MMC framework support 19*c5c1af21SChin Liang See 20*c5c1af21SChin Liang See#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS) 21*c5c1af21SChin Liang See-> The base address of CSR register for DesignWare SDMMC controller 22*c5c1af21SChin Liang See 23*c5c1af21SChin Liang See#define CONFIG_GENERIC_MMC 24*c5c1af21SChin Liang See-> Enable the generic MMC driver 25*c5c1af21SChin Liang See 26*c5c1af21SChin Liang See#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 27*c5c1af21SChin Liang See-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM 28*c5c1af21SChin Liang See 29*c5c1af21SChin Liang See#define CONFIG_DWMMC 30*c5c1af21SChin Liang See-> Enable the common DesignWare SDMMC controller framework 31*c5c1af21SChin Liang See 32*c5c1af21SChin Liang See#define CONFIG_SOCFPGA_DWMMC 33*c5c1af21SChin Liang See-> Enable the SOCFPGA specific driver for DesignWare SDMMC controller 34*c5c1af21SChin Liang See 35*c5c1af21SChin Liang See#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 36*c5c1af21SChin Liang See-> The FIFO depth for SOCFPGA DesignWare SDMMC controller 37*c5c1af21SChin Liang See 38*c5c1af21SChin Liang See#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 39*c5c1af21SChin Liang See-> Phase-shifted clock of sdmmc_clk for controller to drive command and data to 40*c5c1af21SChin Liang Seethe card to meet hold time requirements. SD clock is running at 50MHz and 41*c5c1af21SChin Liang Seedrvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time 42*c5c1af21SChin Liang Seeis 135 / 360 * 20ns = 7.5ns. 43*c5c1af21SChin Liang See 44*c5c1af21SChin Liang See#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 45*c5c1af21SChin Liang See-> Phase-shifted clock of sdmmc_clk used to sample the command and data from 46*c5c1af21SChin Liang Seethe card 47*c5c1af21SChin Liang See 48*c5c1af21SChin Liang See#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4 49*c5c1af21SChin Liang See-> Bus width of data line which either 1, 4 or 8 and based on board routing. 50*c5c1af21SChin Liang See 51*c5c1af21SChin Liang See#define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000 52*c5c1af21SChin Liang See-> The clock rate to controller. Do note the controller have a wrapper which 53*c5c1af21SChin Liang Seedivide the clock from PLL by 4. 54