1NAND FLASH commands and notes 2 3 4See NOTE below!!! 5 6 7# (C) Copyright 2003 8# Dave Ellis, SIXNET, dge@sixnetio.com 9# 10# See file CREDITS for list of people who contributed to this 11# project. 12# 13# This program is free software; you can redistribute it and/or 14# modify it under the terms of the GNU General Public License as 15# published by the Free Software Foundation; either version 2 of 16# the License, or (at your option) any later version. 17# 18# This program is distributed in the hope that it will be useful, 19# but WITHOUT ANY WARRANTY; without even the implied warranty of 20# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21# GNU General Public License for more details. 22# 23# You should have received a copy of the GNU General Public License 24# along with this program; if not, write to the Free Software 25# Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26# MA 02111-1307 USA 27 28Commands: 29 30 nand bad 31 Print a list of all of the bad blocks in the current device. 32 33 nand device 34 Print information about the current NAND device. 35 36 nand device num 37 Make device `num' the current device and print information about it. 38 39 nand erase off size 40 nand erase clean [off size] 41 Erase `size' bytes starting at offset `off'. Only complete erase 42 blocks can be erased. 43 44 If `clean' is specified, a JFFS2-style clean marker is written to 45 each block after it is erased. If `clean' is specified without an 46 offset or size, the entire flash is erased. 47 48 This command will not erase blocks that are marked bad. There is 49 a debug option in cmd_nand.c to allow bad blocks to be erased. 50 Please read the warning there before using it, as blocks marked 51 bad by the manufacturer must _NEVER_ be erased. 52 53 nand info 54 Print information about all of the NAND devices found. 55 56 nand read addr ofs size 57 Read `size' bytes from `ofs' in NAND flash to `addr'. If a page 58 cannot be read because it is marked bad or an uncorrectable data 59 error is found the command stops with an error. 60 61 nand read.jffs2 addr ofs size 62 Like `read', but the data for blocks that are marked bad is read as 63 0xff. This gives a readable JFFS2 image that can be processed by 64 the JFFS2 commands such as ls and fsload. 65 66 nand read.oob addr ofs size 67 Read `size' bytes from the out-of-band data area corresponding to 68 `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of 69 data for one 512-byte page or 2 256-byte pages. There is no check 70 for bad blocks or ECC errors. 71 72 nand write addr ofs size 73 Write `size' bytes from `addr' to `ofs' in NAND flash. If a page 74 cannot be written because it is marked bad or the write fails the 75 command stops with an error. 76 77 nand write.jffs2 addr ofs size 78 Like `write', but blocks that are marked bad are skipped and the 79 is written to the next block instead. This allows writing writing 80 a JFFS2 image, as long as the image is short enough to fit even 81 after skipping the bad blocks. Compact images, such as those 82 produced by mkfs.jffs2 should work well, but loading an image copied 83 from another flash is going to be trouble if there are any bad blocks. 84 85 nand write.oob addr ofs size 86 Write `size' bytes from `addr' to the out-of-band data area 87 corresponding to `ofs' in NAND flash. This is limited to the 16 bytes 88 of data for one 512-byte page or 2 256-byte pages. There is no check 89 for bad blocks. 90 91Configuration Options: 92 93 CFG_CMD_NAND 94 A good one to add to CONFIG_COMMANDS since it enables NAND support. 95 96 CONFIG_MTD_NAND_ECC_JFFS2 97 Define this if you want the Error Correction Code information in 98 the out-of-band data to be formatted to match the JFFS2 file system. 99 CONFIG_MTD_NAND_ECC_YAFFS would be another useful choice for 100 someone to implement. 101 102 CFG_MAX_NAND_DEVICE 103 The maximum number of NAND devices you want to support. 104 105NAND Interface: 106 107 #define NAND_WAIT_READY(nand) 108 Wait until the NAND flash is ready. Typically this would be a 109 loop waiting for the READY/BUSY line from the flash to indicate it 110 it is ready. 111 112 #define WRITE_NAND_COMMAND(d, adr) 113 Write the command byte `d' to the flash at `adr' with the 114 CLE (command latch enable) line true. If your board uses writes to 115 different addresses to control CLE and ALE, you can modify `adr' 116 to be the appropriate address here. If your board uses I/O registers 117 to control them, it is probably better to let NAND_CTL_SETCLE() 118 and company do it. 119 120 #define WRITE_NAND_ADDRESS(d, adr) 121 Write the address byte `d' to the flash at `adr' with the 122 ALE (address latch enable) line true. If your board uses writes to 123 different addresses to control CLE and ALE, you can modify `adr' 124 to be the appropriate address here. If your board uses I/O registers 125 to control them, it is probably better to let NAND_CTL_SETALE() 126 and company do it. 127 128 #define WRITE_NAND(d, adr) 129 Write the data byte `d' to the flash at `adr' with the 130 ALE and CLE lines false. If your board uses writes to 131 different addresses to control CLE and ALE, you can modify `adr' 132 to be the appropriate address here. If your board uses I/O registers 133 to control them, it is probably better to let NAND_CTL_CLRALE() 134 and company do it. 135 136 #define READ_NAND(adr) 137 Read a data byte from the flash at `adr' with the 138 ALE and CLE lines false. If your board uses reads from 139 different addresses to control CLE and ALE, you can modify `adr' 140 to be the appropriate address here. If your board uses I/O registers 141 to control them, it is probably better to let NAND_CTL_CLRALE() 142 and company do it. 143 144 #define NAND_DISABLE_CE(nand) 145 Set CE (Chip Enable) low to enable the NAND flash. 146 147 #define NAND_ENABLE_CE(nand) 148 Set CE (Chip Enable) high to disable the NAND flash. 149 150 #define NAND_CTL_CLRALE(nandptr) 151 Set ALE (address latch enable) low. If ALE control is handled by 152 WRITE_NAND_ADDRESS() this can be empty. 153 154 #define NAND_CTL_SETALE(nandptr) 155 Set ALE (address latch enable) high. If ALE control is handled by 156 WRITE_NAND_ADDRESS() this can be empty. 157 158 #define NAND_CTL_CLRCLE(nandptr) 159 Set CLE (command latch enable) low. If CLE control is handled by 160 WRITE_NAND_ADDRESS() this can be empty. 161 162 #define NAND_CTL_SETCLE(nandptr) 163 Set CLE (command latch enable) high. If CLE control is handled by 164 WRITE_NAND_ADDRESS() this can be empty. 165 166More Definitions: 167 168 These definitions are needed in the board configuration for now, but 169 may really belong in a header file. 170 TODO: Figure which ones are truly configuration settings and rename 171 them to CFG_NAND_... and move the rest somewhere appropriate. 172 173 #define SECTORSIZE 512 174 #define ADDR_COLUMN 1 175 #define ADDR_PAGE 2 176 #define ADDR_COLUMN_PAGE 3 177 #define NAND_ChipID_UNKNOWN 0x00 178 #define NAND_MAX_FLOORS 1 179 #define NAND_MAX_CHIPS 1 180 181 182NOTE: 183===== 184 185We now use a complete rewrite of the NAND code based on what is in 1862.6.12 Linux kernel. 187 188The old NAND handling code has been re-factored and is now confined 189to only board-specific files and - unfortunately - to the DoC code 190(see below). A new configuration variable has been introduced: 191CFG_NAND_LEGACY, which has to be defined in the board config file if 192that board uses legacy code. If CFG_NAND_LEGACY is defined, the board 193specific config.mk file should also have "BOARDLIBS = 194drivers/nand_legacy/libnand_legacy.a". For boards using the new NAND 195approach (PPChameleon and netstar at the moment) no variable is 196necessary, but the config.mk should have "BOARDLIBS = 197drivers/nand/libnand.a". 198 199The necessary changes have been made to all affected boards, and no 200build breakage has been introduced, except for NETTA and NETTA_ISDN 201targets from MAKEALL. This is due to the fact that these two boards 202use JFFS, which has been adopted to use the new NAND, and at the same 203time use NAND in legacy mode. The breakage will disappear when the 204board-specific code is changed to the new NAND. 205 206As mentioned above, the legacy code is still used by the DoC subsystem. 207The consequence of this is that the legacy NAND can't be removed from 208the tree until the DoC is ported to use the new NAND support (or boards 209with DoC will break). 210