1NAND FLASH commands and notes 2 3See NOTE below!!! 4 5# (C) Copyright 2003 6# Dave Ellis, SIXNET, dge@sixnetio.com 7# 8# See file CREDITS for list of people who contributed to this 9# project. 10# 11# This program is free software; you can redistribute it and/or 12# modify it under the terms of the GNU General Public License as 13# published by the Free Software Foundation; either version 2 of 14# the License, or (at your option) any later version. 15# 16# This program is distributed in the hope that it will be useful, 17# but WITHOUT ANY WARRANTY; without even the implied warranty of 18# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19# GNU General Public License for more details. 20# 21# You should have received a copy of the GNU General Public License 22# along with this program; if not, write to the Free Software 23# Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24# MA 02111-1307 USA 25 26Commands: 27 28 nand bad 29 Print a list of all of the bad blocks in the current device. 30 31 nand device 32 Print information about the current NAND device. 33 34 nand device num 35 Make device `num' the current device and print information about it. 36 37 nand erase off|partition size 38 nand erase clean [off|partition size] 39 Erase `size' bytes starting at offset `off'. Alternatively partition 40 name can be specified, in this case size will be eventually limited 41 to not exceed partition size (this behaviour applies also to read 42 and write commands). Only complete erase blocks can be erased. 43 44 If `erase' is specified without an offset or size, the entire flash 45 is erased. If `erase' is specified with partition but without an 46 size, the entire partition is erased. 47 48 If `clean' is specified, a JFFS2-style clean marker is written to 49 each block after it is erased. 50 51 This command will not erase blocks that are marked bad. There is 52 a debug option in cmd_nand.c to allow bad blocks to be erased. 53 Please read the warning there before using it, as blocks marked 54 bad by the manufacturer must _NEVER_ be erased. 55 56 nand info 57 Print information about all of the NAND devices found. 58 59 nand read addr ofs|partition size 60 Read `size' bytes from `ofs' in NAND flash to `addr'. If a page 61 cannot be read because it is marked bad or an uncorrectable data 62 error is found the command stops with an error. 63 64 nand read.jffs2 addr ofs|partition size 65 Like `read', but the data for blocks that are marked bad is read as 66 0xff. This gives a readable JFFS2 image that can be processed by 67 the JFFS2 commands such as ls and fsload. 68 69 nand read.oob addr ofs|partition size 70 Read `size' bytes from the out-of-band data area corresponding to 71 `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of 72 data for one 512-byte page or 2 256-byte pages. There is no check 73 for bad blocks or ECC errors. 74 75 nand write addr ofs|partition size 76 Write `size' bytes from `addr' to `ofs' in NAND flash. If a page 77 cannot be written because it is marked bad or the write fails the 78 command stops with an error. 79 80 nand write.jffs2 addr ofs|partition size 81 Like `write', but blocks that are marked bad are skipped and the 82 data is written to the next block instead. This allows writing 83 a JFFS2 image, as long as the image is short enough to fit even 84 after skipping the bad blocks. Compact images, such as those 85 produced by mkfs.jffs2 should work well, but loading an image copied 86 from another flash is going to be trouble if there are any bad blocks. 87 88 nand write.oob addr ofs|partition size 89 Write `size' bytes from `addr' to the out-of-band data area 90 corresponding to `ofs' in NAND flash. This is limited to the 16 bytes 91 of data for one 512-byte page or 2 256-byte pages. There is no check 92 for bad blocks. 93 94Configuration Options: 95 96 CONFIG_CMD_NAND 97 Enables NAND support and commmands. 98 99 CONFIG_MTD_NAND_ECC_JFFS2 100 Define this if you want the Error Correction Code information in 101 the out-of-band data to be formatted to match the JFFS2 file system. 102 CONFIG_MTD_NAND_ECC_YAFFS would be another useful choice for 103 someone to implement. 104 105 CFG_MAX_NAND_DEVICE 106 The maximum number of NAND devices you want to support. 107 108NAND Interface: 109 110 #define NAND_WAIT_READY(nand) 111 Wait until the NAND flash is ready. Typically this would be a 112 loop waiting for the READY/BUSY line from the flash to indicate it 113 it is ready. 114 115 #define WRITE_NAND_COMMAND(d, adr) 116 Write the command byte `d' to the flash at `adr' with the 117 CLE (command latch enable) line true. If your board uses writes to 118 different addresses to control CLE and ALE, you can modify `adr' 119 to be the appropriate address here. If your board uses I/O registers 120 to control them, it is probably better to let NAND_CTL_SETCLE() 121 and company do it. 122 123 #define WRITE_NAND_ADDRESS(d, adr) 124 Write the address byte `d' to the flash at `adr' with the 125 ALE (address latch enable) line true. If your board uses writes to 126 different addresses to control CLE and ALE, you can modify `adr' 127 to be the appropriate address here. If your board uses I/O registers 128 to control them, it is probably better to let NAND_CTL_SETALE() 129 and company do it. 130 131 #define WRITE_NAND(d, adr) 132 Write the data byte `d' to the flash at `adr' with the 133 ALE and CLE lines false. If your board uses writes to 134 different addresses to control CLE and ALE, you can modify `adr' 135 to be the appropriate address here. If your board uses I/O registers 136 to control them, it is probably better to let NAND_CTL_CLRALE() 137 and company do it. 138 139 #define READ_NAND(adr) 140 Read a data byte from the flash at `adr' with the 141 ALE and CLE lines false. If your board uses reads from 142 different addresses to control CLE and ALE, you can modify `adr' 143 to be the appropriate address here. If your board uses I/O registers 144 to control them, it is probably better to let NAND_CTL_CLRALE() 145 and company do it. 146 147 #define NAND_DISABLE_CE(nand) 148 Set CE (Chip Enable) low to enable the NAND flash. 149 150 #define NAND_ENABLE_CE(nand) 151 Set CE (Chip Enable) high to disable the NAND flash. 152 153 #define NAND_CTL_CLRALE(nandptr) 154 Set ALE (address latch enable) low. If ALE control is handled by 155 WRITE_NAND_ADDRESS() this can be empty. 156 157 #define NAND_CTL_SETALE(nandptr) 158 Set ALE (address latch enable) high. If ALE control is handled by 159 WRITE_NAND_ADDRESS() this can be empty. 160 161 #define NAND_CTL_CLRCLE(nandptr) 162 Set CLE (command latch enable) low. If CLE control is handled by 163 WRITE_NAND_ADDRESS() this can be empty. 164 165 #define NAND_CTL_SETCLE(nandptr) 166 Set CLE (command latch enable) high. If CLE control is handled by 167 WRITE_NAND_ADDRESS() this can be empty. 168 169More Definitions: 170 171 These definitions are needed in the board configuration for now, but 172 may really belong in a header file. 173 TODO: Figure which ones are truly configuration settings and rename 174 them to CFG_NAND_... and move the rest somewhere appropriate. 175 176 #define SECTORSIZE 512 177 #define ADDR_COLUMN 1 178 #define ADDR_PAGE 2 179 #define ADDR_COLUMN_PAGE 3 180 #define NAND_ChipID_UNKNOWN 0x00 181 #define NAND_MAX_FLOORS 1 182 #define NAND_MAX_CHIPS 1 183 184 185NOTE: 186===== 187 188We now use a complete rewrite of the NAND code based on what is in 1892.6.12 Linux kernel. 190 191The old NAND handling code has been re-factored and is now confined 192to only board-specific files and - unfortunately - to the DoC code 193(see below). A new configuration variable has been introduced: 194CFG_NAND_LEGACY, which has to be defined in the board config file if 195that board uses legacy code. 196 197The necessary changes have been made to all affected boards, and no 198build breakage has been introduced, except for NETTA and NETTA_ISDN 199targets from MAKEALL. This is due to the fact that these two boards 200use JFFS, which has been adopted to use the new NAND, and at the same 201time use NAND in legacy mode. The breakage will disappear when the 202board-specific code is changed to the new NAND. 203 204As mentioned above, the legacy code is still used by the DoC subsystem. 205The consequence of this is that the legacy NAND can't be removed from 206the tree until the DoC is ported to use the new NAND support (or boards 207with DoC will break). 208 209 210Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006 211 212JFFS2 related commands: 213 214 implement "nand erase clean" and old "nand erase" 215 using both the new code which is able to skip bad blocks 216 "nand erase clean" additionally writes JFFS2-cleanmarkers in the oob. 217 218 "nand write.jffs2" 219 like "nand write" but skip found bad eraseblocks 220 221 "nand read.jffs2" 222 like "nand read" but skip found bad eraseblocks 223 224Miscellaneous and testing commands: 225 "markbad [offset]" 226 create an artificial bad block (for testing bad block handling) 227 228 "scrub [offset length]" 229 like "erase" but don't skip bad block. Instead erase them. 230 DANGEROUS!!! Factory set bad blocks will be lost. Use only 231 to remove artificial bad blocks created with the "markbad" command. 232 233 234NAND locking command (for chips with active LOCKPRE pin) 235 236 "nand lock" 237 set NAND chip to lock state (all pages locked) 238 239 "nand lock tight" 240 set NAND chip to lock tight state (software can't change locking anymore) 241 242 "nand lock status" 243 displays current locking status of all pages 244 245 "nand unlock [offset] [size]" 246 unlock consecutive area (can be called multiple times for different areas) 247 248 249I have tested the code with board containing 128MiB NAND large page chips 250and 32MiB small page chips. 251