1*887e2ec9SStefan Roese----------------------------- 2*887e2ec9SStefan RoeseNAND boot on PPC440 platforms 3*887e2ec9SStefan Roese----------------------------- 4*887e2ec9SStefan Roese 5*887e2ec9SStefan RoeseThis document describes the U-Boot NAND boot feature as it 6*887e2ec9SStefan Roeseis implemented for the AMCC Sequoia (PPC440EPx) board. 7*887e2ec9SStefan Roese 8*887e2ec9SStefan RoeseThe PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH, 9*887e2ec9SStefan Roesecompletely without NOR FLASH. This can be done by using the NAND 10*887e2ec9SStefan Roeseboot feature of the 440 NAND flash controller (NDFC). 11*887e2ec9SStefan Roese 12*887e2ec9SStefan RoeseHere a short desciption of the different boot stages: 13*887e2ec9SStefan Roese 14*887e2ec9SStefan Roesea) IPL (Initial Program Loader, integrated inside CPU) 15*887e2ec9SStefan Roese------------------------------------------------------ 16*887e2ec9SStefan RoeseWill load first 4k from NAND (SPL) into cache and execute it from there. 17*887e2ec9SStefan Roese 18*887e2ec9SStefan Roeseb) SPL (Secondary Program Loader) 19*887e2ec9SStefan Roese--------------------------------- 20*887e2ec9SStefan RoeseWill load special U-Boot version (NUB) from NAND and execute it. This SPL 21*887e2ec9SStefan Roesehas to fit into 4kByte. It sets up the CPU and configures the SDRAM 22*887e2ec9SStefan Roesecontroller and the NAND controller so that the special U-Boot image can be 23*887e2ec9SStefan Roeseloaded from NAND to SDRAM. 24*887e2ec9SStefan RoeseThis special image is build in the directory "nand_spl". 25*887e2ec9SStefan Roese 26*887e2ec9SStefan Roesec) NUB (NAND U-Boot) 27*887e2ec9SStefan Roese-------------------- 28*887e2ec9SStefan RoeseThis NAND U-Boot (NUB) is a special U-Boot version which can be started 29*887e2ec9SStefan Roesefrom RAM. Therefore it mustn't (re-)configure the SDRAM controller. 30*887e2ec9SStefan Roese 31*887e2ec9SStefan RoeseOn 440EPx the SPL is copied to internal SRAM before the NAND controller 32*887e2ec9SStefan Roeseis set up. While still running from cache, I experienced problems accessing 33*887e2ec9SStefan Roesethe NAND controller. 34*887e2ec9SStefan Roese 35*887e2ec9SStefan Roese 36*887e2ec9SStefan RoeseSeptember 07 2006, Stefan Roese <sr@denx.de> 37