1Driver implementing the fuse API for Freescale's On-Chip OTP Controller (OCOTP) 2on MXC 3 4This IP can be found on the following SoCs: 5 - i.MX6. 6 7Note that this IP is different from albeit similar to the IPs of the same name 8that can be found on the following SoCs: 9 - i.MX23, 10 - i.MX28, 11 - i.MX50. 12 13The section numbers in this file refer to the i.MX6 Reference Manual. 14 15A fuse word contains 32 fuse bit slots, as explained in 46.2.1. 16 17A bank contains 8 fuse word slots, as explained in 46.2.1 and shown by the 18memory map in 46.4. 19 20Some fuse bit or word slots may not have the corresponding fuses actually 21implemented in the fusebox. 22 23See the README files of the SoCs using this driver in order to know the 24conventions used by U-Boot to store some specific data in the fuses, e.g. MAC 25addresses. 26 27Fuse operations: 28 29 Read 30 Read operations are implemented as read accesses to the shadow registers, 31 using "Bankx Wordy" from the memory map in 46.4. This is explained in 32 detail by the first two paragraphs in 46.2.1.2. 33 34 Sense 35 Sense operations are implemented as the direct fusebox read explained by 36 the steps in 46.2.1.2. 37 38 Program 39 Program operations are implemented as explained by the steps in 46.2.1.3. 40 Following this operation, the shadow registers are not reloaded by the 41 hardware. 42 43 Override 44 Override operations are implemented as write accesses to the shadow 45 registers, as explained by the first paragraph in 46.2.1.3. 46 47Configuration: 48 49 CONFIG_MXC_OCOTP 50 Define this to enable the mxc_ocotp driver. 51