1*112fd2ecSBenoît ThébaudeauDriver implementing the fuse API for Freescale's On-Chip OTP Controller (OCOTP) 2*112fd2ecSBenoît Thébaudeauon MXC 3*112fd2ecSBenoît Thébaudeau 4*112fd2ecSBenoît ThébaudeauThis IP can be found on the following SoCs: 5*112fd2ecSBenoît Thébaudeau - i.MX6. 6*112fd2ecSBenoît Thébaudeau 7*112fd2ecSBenoît ThébaudeauNote that this IP is different from albeit similar to the IPs of the same name 8*112fd2ecSBenoît Thébaudeauthat can be found on the following SoCs: 9*112fd2ecSBenoît Thébaudeau - i.MX23, 10*112fd2ecSBenoît Thébaudeau - i.MX28, 11*112fd2ecSBenoît Thébaudeau - i.MX50. 12*112fd2ecSBenoît Thébaudeau 13*112fd2ecSBenoît ThébaudeauThe section numbers in this file refer to the i.MX6 Reference Manual. 14*112fd2ecSBenoît Thébaudeau 15*112fd2ecSBenoît ThébaudeauA fuse word contains 32 fuse bit slots, as explained in 46.2.1. 16*112fd2ecSBenoît Thébaudeau 17*112fd2ecSBenoît ThébaudeauA bank contains 8 fuse word slots, as explained in 46.2.1 and shown by the 18*112fd2ecSBenoît Thébaudeaumemory map in 46.4. 19*112fd2ecSBenoît Thébaudeau 20*112fd2ecSBenoît ThébaudeauSome fuse bit or word slots may not have the corresponding fuses actually 21*112fd2ecSBenoît Thébaudeauimplemented in the fusebox. 22*112fd2ecSBenoît Thébaudeau 23*112fd2ecSBenoît ThébaudeauSee the README files of the SoCs using this driver in order to know the 24*112fd2ecSBenoît Thébaudeauconventions used by U-Boot to store some specific data in the fuses, e.g. MAC 25*112fd2ecSBenoît Thébaudeauaddresses. 26*112fd2ecSBenoît Thébaudeau 27*112fd2ecSBenoît ThébaudeauFuse operations: 28*112fd2ecSBenoît Thébaudeau 29*112fd2ecSBenoît Thébaudeau Read 30*112fd2ecSBenoît Thébaudeau Read operations are implemented as read accesses to the shadow registers, 31*112fd2ecSBenoît Thébaudeau using "Bankx Wordy" from the memory map in 46.4. This is explained in 32*112fd2ecSBenoît Thébaudeau detail by the first two paragraphs in 46.2.1.2. 33*112fd2ecSBenoît Thébaudeau 34*112fd2ecSBenoît Thébaudeau Sense 35*112fd2ecSBenoît Thébaudeau Sense operations are implemented as the direct fusebox read explained by 36*112fd2ecSBenoît Thébaudeau the steps in 46.2.1.2. 37*112fd2ecSBenoît Thébaudeau 38*112fd2ecSBenoît Thébaudeau Program 39*112fd2ecSBenoît Thébaudeau Program operations are implemented as explained by the steps in 46.2.1.3. 40*112fd2ecSBenoît Thébaudeau Following this operation, the shadow registers are not reloaded by the 41*112fd2ecSBenoît Thébaudeau hardware. 42*112fd2ecSBenoît Thébaudeau 43*112fd2ecSBenoît Thébaudeau Override 44*112fd2ecSBenoît Thébaudeau Override operations are implemented as write accesses to the shadow 45*112fd2ecSBenoît Thébaudeau registers, as explained by the first paragraph in 46.2.1.3. 46*112fd2ecSBenoît Thébaudeau 47*112fd2ecSBenoît ThébaudeauConfiguration: 48*112fd2ecSBenoît Thébaudeau 49*112fd2ecSBenoît Thébaudeau CONFIG_MXC_OCOTP 50*112fd2ecSBenoît Thébaudeau Define this to enable the mxc_ocotp driver. 51