1*afa6b551SPrabhakar KushwahaExternal Debug Support 2*afa6b551SPrabhakar Kushwaha---------------------- 3*afa6b551SPrabhakar Kushwaha 4*afa6b551SPrabhakar KushwahaFreescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some 5*afa6b551SPrabhakar Kushwaharestrictions on external debugging (JTAG). In particular, for the debugger to 6*afa6b551SPrabhakar Kushwahabe able to receive control after a single step or breakpoint: 7*afa6b551SPrabhakar Kushwaha - MSR[DE] must be set 8*afa6b551SPrabhakar Kushwaha - A valid opcode must be fetchable, through the MMU, from the debug 9*afa6b551SPrabhakar Kushwaha exception vector (IVPR + IVOR15). 10*afa6b551SPrabhakar Kushwaha 11*afa6b551SPrabhakar KushwahaTo maximize the time during which this requirement is met, U-Boot sets MSR[DE] 12*afa6b551SPrabhakar Kushwahaimmediately on entry and keeps it set. It also uses a temporary TLB to keep a 13*afa6b551SPrabhakar Kushwahamapping to a valid opcode at the debug exception vector, even if we normally 14*afa6b551SPrabhakar Kushwahadon't support exception vectors being used that early, and that's not the area 15*afa6b551SPrabhakar Kushwahawhere U-Boot currently executes from. 16*afa6b551SPrabhakar Kushwaha 17*afa6b551SPrabhakar KushwahaNote that there may still be some small windows where debugging will not work, 18*afa6b551SPrabhakar Kushwahasuch as in between updating IVPR and IVOR15. 19*afa6b551SPrabhakar Kushwaha 20*afa6b551SPrabhakar KushwahaConfig Switches: 21*afa6b551SPrabhakar Kushwaha---------------- 22*afa6b551SPrabhakar Kushwaha 23*afa6b551SPrabhakar KushwahaPlease refer README section "MPC85xx External Debug Support" 24*afa6b551SPrabhakar Kushwaha 25*afa6b551SPrabhakar KushwahaMajor Config Switches during various boot Modes 26*afa6b551SPrabhakar Kushwaha---------------------------------------------- 27*afa6b551SPrabhakar Kushwaha 28*afa6b551SPrabhakar KushwahaNOR boot 29*afa6b551SPrabhakar Kushwaha !defined(CONFIG_SYS_RAMBOOT) 30*afa6b551SPrabhakar KushwahaNOR boot Secure 31*afa6b551SPrabhakar Kushwaha !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 32*afa6b551SPrabhakar KushwahaRAMBOOT(SD, SPI & NAND boot) 33*afa6b551SPrabhakar Kushwaha defined(CONFIG_SYS_RAMBOOT) 34*afa6b551SPrabhakar KushwahaRAMBOOT Secure (SD, SPI & NAND) 35*afa6b551SPrabhakar Kushwaha defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 36*afa6b551SPrabhakar KushwahaNAND SPL BOOT 37*afa6b551SPrabhakar Kushwaha defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL) 38*afa6b551SPrabhakar Kushwaha 39*afa6b551SPrabhakar Kushwaha 40*afa6b551SPrabhakar KushwahaTLB Entries during u-boot execution 41*afa6b551SPrabhakar Kushwaha----------------------------------- 42*afa6b551SPrabhakar Kushwaha 43*afa6b551SPrabhakar KushwahaNote: Sequence number is in order of execution 44*afa6b551SPrabhakar Kushwaha 45*afa6b551SPrabhakar KushwahaA) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 46*afa6b551SPrabhakar Kushwaha 47*afa6b551SPrabhakar Kushwaha 1) TLB entry to overcome e500 v1/v2 debug restriction 48*afa6b551SPrabhakar Kushwaha Location : Label "_start_e500" 49*afa6b551SPrabhakar Kushwaha TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB 50*afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE 51*afa6b551SPrabhakar Kushwaha Properties : 256K, AS0, I, IPROT 52*afa6b551SPrabhakar Kushwaha 53*afa6b551SPrabhakar Kushwaha 2) TLB entry for working in AS1 54*afa6b551SPrabhakar Kushwaha Location : Label "create_init_ram_area" 55*afa6b551SPrabhakar Kushwaha TLB Entry : 15 56*afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE 57*afa6b551SPrabhakar Kushwaha Properties : 1M, AS1, I, G, IPROT 58*afa6b551SPrabhakar Kushwaha 59*afa6b551SPrabhakar Kushwaha 3) TLB entry for the stack during AS1 60*afa6b551SPrabhakar Kushwaha Location : Lable "create_init_ram_area" 61*afa6b551SPrabhakar Kushwaha TLB Entry : 14 62*afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR 63*afa6b551SPrabhakar Kushwaha Properties : 16K, AS1, IPROT 64*afa6b551SPrabhakar Kushwaha 65*afa6b551SPrabhakar Kushwaha 4) TLB entry for CCSRBAR during AS1 execution 66*afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f 67*afa6b551SPrabhakar Kushwaha TLB Entry : 13 68*afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR 69*afa6b551SPrabhakar Kushwaha Properties : 1M, AS1, I, G 70*afa6b551SPrabhakar Kushwaha 71*afa6b551SPrabhakar Kushwaha 5) Invalidate unproctected TLB Entries 72*afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f 73*afa6b551SPrabhakar Kushwaha Invalidated: 13 74*afa6b551SPrabhakar Kushwaha 75*afa6b551SPrabhakar Kushwaha 6) Create TLB entries as per boards/freescale/<board>/tlb.c 76*afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f --> init_tlbs() 77*afa6b551SPrabhakar Kushwaha Properties : ..., AS0, ... 78*afa6b551SPrabhakar Kushwaha Please note It can overwrites previous TLB Entries. 79*afa6b551SPrabhakar Kushwaha 80*afa6b551SPrabhakar Kushwaha 7) Disable TLB Entries of AS1 81*afa6b551SPrabhakar Kushwaha Location : cpu_init_f --> disable_tlb() 82*afa6b551SPrabhakar Kushwaha Disable : 15, 14 83*afa6b551SPrabhakar Kushwaha 84*afa6b551SPrabhakar Kushwaha 8) Update Flash's TLB entry 85*afa6b551SPrabhakar Kushwaha Location : Board_init_r 86*afa6b551SPrabhakar Kushwaha TLB entry : Search from TLB entries 87*afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS 88*afa6b551SPrabhakar Kushwaha Properties : Board specific size, AS0, I, G, IPROT 89*afa6b551SPrabhakar Kushwaha 90*afa6b551SPrabhakar Kushwaha 91*afa6b551SPrabhakar KushwahaB) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 92*afa6b551SPrabhakar Kushwaha 93*afa6b551SPrabhakar Kushwaha 1) TLB entry to overcome e500 v1/v2 debug restriction 94*afa6b551SPrabhakar Kushwaha Location : Label "_start_e500" 95*afa6b551SPrabhakar Kushwaha TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB 96*afa6b551SPrabhakar Kushwaha#if defined(CONFIG_SECURE_BOOT) 97*afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW 98*afa6b551SPrabhakar Kushwaha Properties : 1M, AS1, I, G, IPROT 99*afa6b551SPrabhakar Kushwaha#else 100*afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 101*afa6b551SPrabhakar Kushwaha Properties : 4M, AS0, I, G, IPROT 102*afa6b551SPrabhakar Kushwaha#endif 103*afa6b551SPrabhakar Kushwaha 104*afa6b551SPrabhakar Kushwaha 2) TLB entry for working in AS1 105*afa6b551SPrabhakar Kushwaha Location : Label "create_init_ram_area" 106*afa6b551SPrabhakar Kushwaha TLB Entry : 15 107*afa6b551SPrabhakar Kushwaha#if defined(CONFIG_SECURE_BOOT) 108*afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW 109*afa6b551SPrabhakar Kushwaha Properties : 1M, AS1, I, G, IPROT 110*afa6b551SPrabhakar Kushwaha#else 111*afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 112*afa6b551SPrabhakar Kushwaha Properties : 4M, AS1, I, G, IPROT 113*afa6b551SPrabhakar Kushwaha#endif 114*afa6b551SPrabhakar Kushwaha 115*afa6b551SPrabhakar Kushwaha 3) TLB entry for the stack during AS1 116*afa6b551SPrabhakar Kushwaha Location : Lable "create_init_ram_area" 117*afa6b551SPrabhakar Kushwaha TLB Entry : 14 118*afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR 119*afa6b551SPrabhakar Kushwaha Properties : 16K, AS1, IPROT 120*afa6b551SPrabhakar Kushwaha 121*afa6b551SPrabhakar Kushwaha 4) TLB entry for CCSRBAR during AS1 execution 122*afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f 123*afa6b551SPrabhakar Kushwaha TLB Entry : 13 124*afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR 125*afa6b551SPrabhakar Kushwaha Properties : 1M, AS1, I, G 126*afa6b551SPrabhakar Kushwaha 127*afa6b551SPrabhakar Kushwaha 5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399 128*afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f 129*afa6b551SPrabhakar Kushwaha TLB Entry : 9 130*afa6b551SPrabhakar Kushwaha EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR 131*afa6b551SPrabhakar Kushwaha Properties : 1M, AS1, I 132*afa6b551SPrabhakar Kushwaha 133*afa6b551SPrabhakar Kushwaha 6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr 134*afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f --> setup_ifc 135*afa6b551SPrabhakar Kushwaha TLB Entry : Get Flash TLB 136*afa6b551SPrabhakar Kushwaha EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys 137*afa6b551SPrabhakar Kushwaha Properties : 4M, AS1, I, G, IPROT 138*afa6b551SPrabhakar Kushwaha 139*afa6b551SPrabhakar Kushwaha 7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction 140*afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f --> setup_ifc 141*afa6b551SPrabhakar Kushwaha TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB 142*afa6b551SPrabhakar Kushwaha EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys 143*afa6b551SPrabhakar Kushwaha Properties : 4M, AS0, I, G, IPROT 144*afa6b551SPrabhakar Kushwaha 145*afa6b551SPrabhakar Kushwaha 8) Invalidate unproctected TLB Entries 146*afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f 147*afa6b551SPrabhakar Kushwaha Invalidated: 13, 9 148*afa6b551SPrabhakar Kushwaha 149*afa6b551SPrabhakar Kushwaha 9) Create TLB entries as per boards/freescale/<board>/tlb.c 150*afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f --> init_tlbs() 151*afa6b551SPrabhakar Kushwaha Properties : ..., AS0, ... 152*afa6b551SPrabhakar Kushwaha Note: It can overwrites previous TLB Entries 153*afa6b551SPrabhakar Kushwaha 154*afa6b551SPrabhakar Kushwaha 10) Disable TLB Entries of AS1 155*afa6b551SPrabhakar Kushwaha Location : cpu_init_f --> disable_tlb() 156*afa6b551SPrabhakar Kushwaha Disable : 15, 14 157*afa6b551SPrabhakar Kushwaha 158*afa6b551SPrabhakar Kushwaha 11) Create DDR's TLB entriy 159*afa6b551SPrabhakar Kushwaha Location : Board_init_f -> init_func_ram -> initdram 160*afa6b551SPrabhakar Kushwaha TLB entry : Search free TLB entry 161*afa6b551SPrabhakar Kushwaha 162*afa6b551SPrabhakar Kushwaha 12) Update Flash's TLB entry 163*afa6b551SPrabhakar Kushwaha Location : Board_init_r 164*afa6b551SPrabhakar Kushwaha TLB entry : Search from TLB entries 165*afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS 166*afa6b551SPrabhakar Kushwaha Properties : Board specific size, AS0, I, G, IPROT 167