1Spin table in cache 2===================================== 3As specified by ePAPR v1.1, the spin table needs to be in cached memory. After 4DDR is initialized and U-Boot relocates itself into DDR, the spin table is 5accessible for core 0. It is part of release.S, within 4KB range after 6__secondary_start_page. For other cores to use the spin table, the booting 7process is described below: 8 9Core 0 sets up the reset page on the top 4K of memory (or 4GB if total memory 10is more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless of 11the physical address of this page, with WIMGE=0b01010. Core 0 also enables boot 12page translation for secondary cores to use this page of memory. Then 4KB 13memory is copied from __secondary_start_page to the boot page, after flusing 14cache because this page is mapped as normal DDR. Before copying the reset page, 15core 0 puts the physical address of the spin table (which is in release.S and 16relocated to the top of mapped memory) into a variable __spin_table_addr so 17that secondary cores can see it. 18 19When secondary cores boot up from 0xffff_f000 page, they only have one default 20TLB. While booting, they set up another TLB in AS=1 space and jump into 21the new space. The new TLB covers the physical address of the spin table page, 22with WIMGE =0b00100. Now secondary cores can keep polling the spin table 23without stress DDR bus because both the code and the spin table is in cache. 24 25For the above to work, DDR has to set the 'M' bit of WIMGE, in order to keep 26cache coherence. 27