1*ffd06e02SYork SunSpin table in cache 2*ffd06e02SYork Sun===================================== 3*ffd06e02SYork SunAs specified by ePAPR v1.1, the spin table needs to be in cached memory. After 4*ffd06e02SYork SunDDR is initialized and U-boot relocates itself into DDR, the spin table is 5*ffd06e02SYork Sunaccessible for core 0. It is part of release.S, within 4KB range after 6*ffd06e02SYork Sun__secondary_start_page. For other cores to use the spin table, the booting 7*ffd06e02SYork Sunprocess is described below: 8*ffd06e02SYork Sun 9*ffd06e02SYork SunCore 0 sets up the reset page on the top 4K of memory (or 4GB if total memory 10*ffd06e02SYork Sunis more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless of 11*ffd06e02SYork Sunthe physical address of this page, with WIMGE=0b01010. Core 0 also enables boot 12*ffd06e02SYork Sunpage translation for secondary cores to use this page of memory. Then 4KB 13*ffd06e02SYork Sunmemory is copied from __secondary_start_page to the boot page, after flusing 14*ffd06e02SYork Suncache because this page is mapped as normal DDR. Before copying the reset page, 15*ffd06e02SYork Suncore 0 puts the physical address of the spin table (which is in release.S and 16*ffd06e02SYork Sunrelocated to the top of mapped memory) into a variable __spin_table_addr so 17*ffd06e02SYork Sunthat secondary cores can see it. 18*ffd06e02SYork Sun 19*ffd06e02SYork SunWhen secondary cores boot up from 0xffff_f000 page, they only have one default 20*ffd06e02SYork SunTLB. While booting, they set up another TLB in AS=1 space and jump into 21*ffd06e02SYork Sunthe new space. The new TLB covers the physical address of the spin table page, 22*ffd06e02SYork Sunwith WIMGE =0b00100. Now secondary cores can keep polling the spin table 23*ffd06e02SYork Sunwithout stress DDR bus because both the code and the spin table is in cache. 24*ffd06e02SYork Sun 25*ffd06e02SYork SunFor the above to work, DDR has to set the 'M' bit of WIMGE, in order to keep 26*ffd06e02SYork Suncache coherence. 27