1 2Table of interleaving modes supported in cpu/8xxx/ddr/ 3====================================================== 4 +-------------+---------------------------------------------------------+ 5 | | Rank Interleaving | 6 | +--------+-----------+-----------+------------+-----------+ 7 |Memory | | | | 2x2 | 4x1 | 8 |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ | 9 |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} | 10 +-------------+--------+-----------+-----------+------------+-----------+ 11 |None | Yes | Yes | Yes | Yes | Yes | 12 +-------------+--------+-----------+-----------+------------+-----------+ 13 |Cacheline | Yes | Yes | No | No, Only(*)| Yes | 14 | |CS0 Only| | | {CS0+CS1} | | 15 +-------------+--------+-----------+-----------+------------+-----------+ 16 |Page | Yes | Yes | No | No, Only(*)| Yes | 17 | |CS0 Only| | | {CS0+CS1} | | 18 +-------------+--------+-----------+-----------+------------+-----------+ 19 |Bank | Yes | Yes | No | No, Only(*)| Yes | 20 | |CS0 Only| | | {CS0+CS1} | | 21 +-------------+--------+-----------+-----------+------------+-----------+ 22 |Superbank | No | Yes | No | No, Only(*)| Yes | 23 | | | | | {CS0+CS1} | | 24 +-------------+--------+-----------+-----------+------------+-----------+ 25 (*) Although the hardware can be configured with memory controller 26 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1} 27 from each controller. {CS2+CS3} on each controller are only rank 28 interleaved on that controller. 29 30 For memory controller interleaving, identical DIMMs are suggested. Software 31 doesn't check the size or organization of interleaved DIMMs. 32 33The ways to configure the ddr interleaving mode 34============================================== 351. In board header file(e.g.MPC8572DS.h), add default interleaving setting 36 under "CONFIG_EXTRA_ENV_SETTINGS", like: 37 #define CONFIG_EXTRA_ENV_SETTINGS \ 38 "hwconfig=fsl_ddr:ctlr_intlv=bank" \ 39 ...... 40 412. Run u-boot "setenv" command to configure the memory interleaving mode. 42 Either numerical or string value is accepted. 43 44 # disable memory controller interleaving 45 setenv hwconfig "fsl_ddr:ctlr_intlv=null" 46 47 # cacheline interleaving 48 setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline" 49 50 # page interleaving 51 setenv hwconfig "fsl_ddr:ctlr_intlv=page" 52 53 # bank interleaving 54 setenv hwconfig "fsl_ddr:ctlr_intlv=bank" 55 56 # superbank 57 setenv hwconfig "fsl_ddr:ctlr_intlv=superbank" 58 59 # disable bank (chip-select) interleaving 60 setenv hwconfig "fsl_ddr:bank_intlv=null" 61 62 # bank(chip-select) interleaving cs0+cs1 63 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1" 64 65 # bank(chip-select) interleaving cs2+cs3 66 setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3" 67 68 # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2) 69 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3" 70 71 # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) 72 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" 73 74Memory controller address hashing 75================================== 76If the DDR controller supports address hashing, it can be enabled by hwconfig. 77 78Syntax is: 79hwconfig=fsl_ddr:addr_hash=true 80 81Memory controller ECC on/off 82============================ 83If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC, 84ECC can be turned on/off by hwconfig. 85 86Syntax is 87hwconfig=fsl_ddr:ecc=off 88 89Memory testing options for mpc85xx 90================================== 911. Memory test can be done once U-boot prompt comes up using mtest, or 922. Memory test can be done with Power-On-Self-Test function, activated at 93 compile time. 94 95 In order to enable the POST memory test, CONFIG_POST needs to be 96 defined in board configuraiton header file. By default, POST memory test 97 performs a fast test. A slow test can be enabled by changing the flag at 98 compiling time. To test memory bigger than 2GB, 36BIT support is needed. 99 Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB 100 window to physical address so that all physical memory can be tested. 101 102Combination of hwconfig 103======================= 104Hwconfig can be combined with multiple parameters, for example, on a supported 105platform 106 107hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on 108 109Table for dynamic ODT for DDR3 110============================== 111For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may 112be needed, depending on the configuration. The numbers in the following tables are 113in Ohms. 114 115* denotes dynamic ODT 116 117Two slots system 118+-----------------------+----------+---------------+-----------------------------+-----------------------------+ 119| Configuration | |DRAM controller| Slot 1 | Slot 2 | 120+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+ 121| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 | 122+ Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+ 123| | | | | | Write | Read | Write | Read | Write | Read | Write | Read | 124+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 125| | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 | 126| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 127| | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off | 128+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 129| | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | | 130| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 131| | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | | 132+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 133| | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 | 134|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 135| | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off | 136+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 137| | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | | 138|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 139| | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | | 140+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 141| Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | | 142+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 143| Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off | 144+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 145|Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | | 146+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 147| Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | | 148+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 149 150Single slot system 151+-------------+------------+---------------+-----------------------------+-----------------------------+ 152| | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 | 153|Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+ 154| | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read | 155+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 156| | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off | 157| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 158| | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off | 159| Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 160| | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off | 161| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 162| | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off | 163+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 164| | R1 | off | 75 | 40 | off | off | off | 165| Dual Rank |------------+-------+-------+-------+------+-------+------+ 166| | R2 | off | 75 | 40 | off | off | off | 167+-------------+------------+-------+-------+-------+------+-------+------+ 168| Single Rank | R1 | off | 75 | 40 | off | 169+-------------+------------+-------+-------+-------+------+ 170 171Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf 172 http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf 173