xref: /openbmc/u-boot/doc/README.fsl-ddr (revision 79e4e6480b359cb28129cecfa2cae0ef9cccf803) 
1
2Table of interleaving modes supported in cpu/8xxx/ddr/
3======================================================
4  +-------------+---------------------------------------------------------+
5  |             |                   Rank Interleaving                     |
6  |             +--------+-----------+-----------+------------+-----------+
7  |Memory       |        |           |           |    2x2     |    4x1    |
8  |Controller   |  None  | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
9  |Interleaving |        | {CS0+CS1} | {CS2+CS3} | {CS2+CS3}  |  CS2+CS3} |
10  +-------------+--------+-----------+-----------+------------+-----------+
11  |None         |  Yes   | Yes       | Yes       | Yes        | Yes       |
12  +-------------+--------+-----------+-----------+------------+-----------+
13  |Cacheline    |  Yes   | Yes       | No        | No, Only(*)| Yes       |
14  |             |CS0 Only|           |           | {CS0+CS1}  |           |
15  +-------------+--------+-----------+-----------+------------+-----------+
16  |Page         |  Yes   | Yes       | No        | No, Only(*)| Yes       |
17  |             |CS0 Only|           |           | {CS0+CS1}  |           |
18  +-------------+--------+-----------+-----------+------------+-----------+
19  |Bank         |  Yes   | Yes       | No        | No, Only(*)| Yes       |
20  |             |CS0 Only|           |           | {CS0+CS1}  |           |
21  +-------------+--------+-----------+-----------+------------+-----------+
22  |Superbank    |  No    | Yes       | No        | No, Only(*)| Yes       |
23  |             |        |           |           | {CS0+CS1}  |           |
24  +-------------+--------+-----------+-----------+------------+-----------+
25 (*) Although the hardware can be configured with memory controller
26 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
27 from each controller. {CS2+CS3} on each controller are only rank
28 interleaved on that controller.
29
30The ways to configure the ddr interleaving mode
31==============================================
321. In board header file(e.g.MPC8572DS.h), add default interleaving setting
33   under "CONFIG_EXTRA_ENV_SETTINGS", like:
34	#define CONFIG_EXTRA_ENV_SETTINGS				\
35	 "hwconfig=fsl_ddr:ctlr_intlv=bank"			\
36	 ......
37
382. Run u-boot "setenv" command to configure the memory interleaving mode.
39   Either numerical or string value is accepted.
40
41  # disable memory controller interleaving
42  setenv hwconfig "fsl_ddr:ctlr_intlv=null"
43
44  # cacheline interleaving
45  setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
46
47  # page interleaving
48  setenv hwconfig "fsl_ddr:ctlr_intlv=page"
49
50  # bank interleaving
51  setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
52
53  # superbank
54  setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
55
56  # disable bank (chip-select) interleaving
57  setenv hwconfig "fsl_ddr:bank_intlv=null"
58
59  # bank(chip-select) interleaving cs0+cs1
60  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
61
62  # bank(chip-select) interleaving cs2+cs3
63  setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
64
65  # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3)  (2x2)
66  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
67
68  # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
69  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
70
71  The above memory controller interleaving and bank interleaving can be mixed. The syntax is
72  setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1"
73