xref: /openbmc/u-boot/doc/README.fsl-ddr (revision 5187d8dd) 
1
2Table of interleaving modes supported in cpu/8xxx/ddr/
3======================================================
4  +-------------+---------------------------------------------------------+
5  |		|		    Rank Interleaving			  |
6  |		+--------+-----------+-----------+------------+-----------+
7  |Memory	|	 |	     |		 |    2x2     |    4x1	  |
8  |Controller	|  None  | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
9  |Interleaving |	 | {CS0+CS1} | {CS2+CS3} | {CS2+CS3}  |  CS2+CS3} |
10  +-------------+--------+-----------+-----------+------------+-----------+
11  |None		|  Yes	 | Yes	     | Yes	 | Yes	      | Yes	  |
12  +-------------+--------+-----------+-----------+------------+-----------+
13  |Cacheline	|  Yes	 | Yes	     | No	 | No, Only(*)| Yes	  |
14  |		|CS0 Only|	     |		 | {CS0+CS1}  |		  |
15  +-------------+--------+-----------+-----------+------------+-----------+
16  |Page		|  Yes	 | Yes	     | No	 | No, Only(*)| Yes	  |
17  |		|CS0 Only|	     |		 | {CS0+CS1}  |		  |
18  +-------------+--------+-----------+-----------+------------+-----------+
19  |Bank		|  Yes	 | Yes	     | No	 | No, Only(*)| Yes	  |
20  |		|CS0 Only|	     |		 | {CS0+CS1}  |		  |
21  +-------------+--------+-----------+-----------+------------+-----------+
22  |Superbank	|  No	 | Yes	     | No	 | No, Only(*)| Yes	  |
23  |		|	 |	     |		 | {CS0+CS1}  |		  |
24  +-------------+--------+-----------+-----------+------------+-----------+
25 (*) Although the hardware can be configured with memory controller
26 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
27 from each controller. {CS2+CS3} on each controller are only rank
28 interleaved on that controller.
29
30 For memory controller interleaving, identical DIMMs are suggested. Software
31 doesn't check the size or organization of interleaved DIMMs.
32
33The ways to configure the ddr interleaving mode
34==============================================
351. In board header file(e.g.MPC8572DS.h), add default interleaving setting
36   under "CONFIG_EXTRA_ENV_SETTINGS", like:
37	#define CONFIG_EXTRA_ENV_SETTINGS				\
38	 "hwconfig=fsl_ddr:ctlr_intlv=bank"			\
39	 ......
40
412. Run u-boot "setenv" command to configure the memory interleaving mode.
42   Either numerical or string value is accepted.
43
44  # disable memory controller interleaving
45  setenv hwconfig "fsl_ddr:ctlr_intlv=null"
46
47  # cacheline interleaving
48  setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
49
50  # page interleaving
51  setenv hwconfig "fsl_ddr:ctlr_intlv=page"
52
53  # bank interleaving
54  setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
55
56  # superbank
57  setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
58
59  # disable bank (chip-select) interleaving
60  setenv hwconfig "fsl_ddr:bank_intlv=null"
61
62  # bank(chip-select) interleaving cs0+cs1
63  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
64
65  # bank(chip-select) interleaving cs2+cs3
66  setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
67
68  # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3)  (2x2)
69  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
70
71  # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
72  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
73
74Memory controller address hashing
75==================================
76If the DDR controller supports address hashing, it can be enabled by hwconfig.
77
78Syntax is:
79hwconfig=fsl_ddr:addr_hash=true
80
81Memory controller ECC on/off
82============================
83If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC,
84ECC can be turned on/off by hwconfig.
85
86Syntax is
87hwconfig=fsl_ddr:ecc=off
88
89Memory testing options for mpc85xx
90==================================
911. Memory test can be done once U-boot prompt comes up using mtest, or
922. Memory test can be done with Power-On-Self-Test function, activated at
93   compile time.
94
95   In order to enable the POST memory test, CONFIG_POST needs to be
96   defined in board configuraiton header file. By default, POST memory test
97   performs a fast test. A slow test can be enabled by changing the flag at
98   compiling time. To test memory bigger than 2GB, 36BIT support is needed.
99   Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
100   window to physical address so that all physical memory can be tested.
101
102Combination of hwconfig
103=======================
104Hwconfig can be combined with multiple parameters, for example, on a supported
105platform
106
107hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
108
109Table for dynamic ODT for DDR3
110==============================
111For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may
112be needed, depending on the configuration. The numbers in the following tables are
113in Ohms.
114
115* denotes dynamic ODT
116
117Two slots system
118+-----------------------+----------+---------------+-----------------------------+-----------------------------+
119|     Configuration	|	   |DRAM controller|	       Slot 1		 |	      Slot 2	       |
120+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
121|	    |		|	   |	   |	   |	 Rank 1   |	Rank 2	 |   Rank 1	|    Rank 2    |
122+  Slot 1   |	Slot 2	|Write/Read| Write | Read  |-------+------+-------+------+-------+------+-------+------+
123|	    |		|	   |	   |	   | Write | Read | Write | Read | Write | Read | Write | Read |
124+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
125|	    |		|  Slot 1  |  off  | 75    | 120   | off  | off   | off  | off	 | off	| 30	| 30   |
126| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
127|	    |		|  Slot 2  |  off  | 75    | off   | off  | 30	  | 30	 | 120	 | off	| off	| off  |
128+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
129|	    |		|  Slot 1  |  off  | 75    | 120   | off  | off   | off  | 20	 | 20	|	|      |
130| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
131|	    |		|  Slot 2  |  off  | 75    | off   | off  | 20	  | 20	 | 120	*| off	|	|      |
132+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
133|	    |		|  Slot 1  |  off  | 75    | 120  *| off  |	  |	 | off	 | off	| 20	| 20   |
134|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
135|	    |		|  Slot 2  |  off  | 75    | 20    | 20   |	  |	 | 120	 | off	| off	| off  |
136+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
137|	    |		|  Slot 1  |  off  | 75    | 120  *| off  |	  |	 | 30	 | 30	|	|      |
138|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
139|	    |		|  Slot 2  |  off  | 75    | 30    | 30   |	  |	 | 120	*| off	|	|      |
140+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
141| Dual Rank |	Empty	|  Slot 1  |  off  | 75    | 40    | off  | off   | off  |	 |	|	|      |
142+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
143|   Empty   | Dual Rank |  Slot 2  |  off  | 75    |	   |	  |	  |	 | 40	 | off	| off	| off  |
144+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
145|Single Rank|	Empty	|  Slot 1  |  off  | 75    | 40    | off  |	  |	 |	 |	|	|      |
146+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
147|   Empty   |Single Rank|  Slot 2  |  off  | 75    |	   |	  |	  |	 | 40	 | off	|	|      |
148+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
149
150Single slot system
151+-------------+------------+---------------+-----------------------------+-----------------------------+
152|	      |		   |DRAM controller|	 Rank 1   |    Rank 2	 |    Rank 3	|    Rank 4    |
153|Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+
154|	      |		   | Write | Read  | Write | Read | Write | Read | Write | Read | Write | Read |
155+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
156|	      |   R1	   | off   | 75    | 120  *| off  | off   | off  | 20	 | 20	| off	| off  |
157|	      |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
158|	      |   R2	   | off   | 75    | off   | 20   | 120   | off  | 20	 | 20	| off	| off  |
159|  Quad Rank  |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
160|	      |   R3	   | off   | 75    | 20    | 20   | off   | off  | 120	*| off	| off	| off  |
161|	      |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
162|	      |   R4	   | off   | 75    | 20    | 20   | off   | off  | off	 | 20	| 120	| off  |
163+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
164|	      |   R1	   | off   | 75    | 40    | off  | off   | off  |
165|  Dual Rank  |------------+-------+-------+-------+------+-------+------+
166|	      |   R2	   | off   | 75    | 40    | off  | off   | off  |
167+-------------+------------+-------+-------+-------+------+-------+------+
168| Single Rank |   R1	   | off   | 75    | 40    | off  |
169+-------------+------------+-------+-------+-------+------+
170
171Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf
172	  http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf
173
174
175Table for ODT for DDR2
176======================
177Two slots system
178+-----------------------+----------+---------------+-----------------------------+-----------------------------+
179|     Configuration     |          |DRAM controller|           Slot 1            |            Slot 2           |
180+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
181|           |           |          |       |       |     Rank 1   |     Rank 2   |   Rank 1     |    Rank 2    |
182+  Slot 1   |   Slot 2  |Write/Read| Write | Read  |-------+------+-------+------+-------+------+-------+------+
183|           |           |          |       |       | Write | Read | Write | Read | Write | Read | Write | Read |
184+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
185|           |           |  Slot 1  |  off  | 150   | off   | off  | off   | off  | 75    | 75   | off   | off  |
186| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
187|           |           |  Slot 2  |  off  | 150   | 75    | 75   | off   | off  | off   | off  | off   | off  |
188+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
189|           |           |  Slot 1  |  off  | 150   | off   | off  | off   | off  | 75    | 75   |       |      |
190| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
191|           |           |  Slot 2  |  off  | 150   | 75    | 75   | off   | off  | off   | off  |       |      |
192+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
193|           |           |  Slot 1  |  off  | 150   | off   | off  |       |      | 75    | 75   | off   | off  |
194|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
195|           |           |  Slot 2  |  off  | 150   | 75    | 75   |       |      | off   | off  | off   | off  |
196+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
197|           |           |  Slot 1  |  off  | 150   | off   | off  |       |      | 75    | 75   |       |      |
198|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
199|           |           |  Slot 2  |  off  | 150   | 75    | 75   |       |      | off   | off  |       |      |
200+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
201| Dual Rank |   Empty   |  Slot 1  |  off  | 75    | 150   | off  | off   | off  |       |      |       |      |
202+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
203|   Empty   | Dual Rank |  Slot 2  |  off  | 75    |       |      |       |      | 150   | off  | off   | off  |
204+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
205|Single Rank|   Empty   |  Slot 1  |  off  | 75    | 150   | off  |       |      |       |      |       |      |
206+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
207|   Empty   |Single Rank|  Slot 2  |  off  | 75    |       |      |       |      | 150   | off  |       |      |
208+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
209
210Single slot system
211+-------------+------------+---------------+-----------------------------+
212|             |            |DRAM controller|     Rank 1   |    Rank 2    |
213|Configuration| Write/Read |-------+-------+-------+------+-------+------+
214|             |            | Write | Read  | Write | Read | Write | Read |
215+-------------+------------+-------+-------+-------+------+-------+------+
216|             |   R1       | off   | 75    | 150   | off  | off   | off  |
217|  Dual Rank  |------------+-------+-------+-------+------+-------+------+
218|             |   R2       | off   | 75    | 150   | off  | off   | off  |
219+-------------+------------+-------+-------+-------+------+-------+------+
220| Single Rank |   R1       | off   | 75    | 150   | off  |
221+-------------+------------+-------+-------+-------+------+
222
223Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf
224
225
226Interactive DDR debugging
227===========================
228
229For DDR parameter tuning up and debugging, the interactive DDR debugging can
230be activated by saving an environment variable "ddr_interactive". The value
231doesn't matter. Once activated, U-boot prompts "FSL DDR>" before enabling DDR
232controller. The available commands can be seen by typing "help".
233
234The example flow of using interactive debugging is
235type command "compute" to calculate the parameters from the default
236type command "print" with arguments to show SPD, options, registers
237type command "edit" with arguments to change any if desired
238type command "go" to continue calculation and enable DDR controller
239type command "reset" to reset the board
240type command "recompute" to reload SPD and start over
241
242Note, check "next_step" to show the flow. For example, after edit opts, the
243next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is
244STEP_PROGRAM_REGS. Upon issuing command "go", DDR controller will be enabled
245with current setting without further calculation.
246
247The detail syntax for each commands are
248
249print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
250	c<n>		- the controller number, eg. c0, c1
251	d<n>		- the DIMM number, eg. d0, d1
252	spd		- print SPD data
253	dimmparms	- DIMM paramaters, calcualted from SPD
254	commonparms	- lowest common parameters for all DIMMs
255	opts		- options
256	addresses	- address assignment (not implemented yet)
257	regs		- controller registers
258
259edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value>
260	c<n>		- the controller number, eg. c0, c1
261	d<n>		- the DIMM number, eg. d0, d1
262	spd		- print SPD data
263	dimmparms	- DIMM paramaters, calcualted from SPD
264	commonparms	- lowest common parameters for all DIMMs
265	opts		- options
266	addresses	- address assignment (not implemented yet)
267	regs		- controller registers
268	<element>	- name of the modified element
269			  byte number if the object is SPD
270	<value>		- decimal or heximal (prefixed with 0x) numbers
271
272reset
273	no arguement	- reset the board
274
275recompute
276	no argument	- reload SPD and start over
277
278compute
279	no argument	- recompute from current next_step
280
281next_step
282	no argument	- show current next_step
283
284help
285	no argument	- print a list of all commands
286
287go
288	no argument	- program memory controller(s) and continue with U-boot
289
290Examples of debugging flow
291
292	FSL DDR>compute
293	Detected UDIMM UG51U6400N8SU-ACF
294	SL DDR>print
295	print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
296	FSL DDR>print dimmparms
297	DIMM parameters:  Controller=0 DIMM=0
298	DIMM organization parameters:
299	module part name = UG51U6400N8SU-ACF
300	rank_density = 2147483648 bytes (2048 megabytes)
301	capacity = 4294967296 bytes (4096 megabytes)
302	burst_lengths_bitmask = 0C
303	base_addresss = 0 (00000000 00000000)
304	n_ranks = 2
305	data_width = 64
306	primary_sdram_width = 64
307	ec_sdram_width = 0
308	registered_dimm = 0
309	n_row_addr = 15
310	n_col_addr = 10
311	edc_config = 0
312	n_banks_per_sdram_device = 8
313	tCKmin_X_ps = 1500
314	tCKmin_X_minus_1_ps = 0
315	tCKmin_X_minus_2_ps = 0
316	tCKmax_ps = 0
317	caslat_X = 960
318	tAA_ps = 13125
319	caslat_X_minus_1 = 0
320	caslat_X_minus_2 = 0
321	caslat_lowest_derated = 0
322	tRCD_ps = 13125
323	tRP_ps = 13125
324	tRAS_ps = 36000
325	tWR_ps = 15000
326	tWTR_ps = 7500
327	tRFC_ps = 160000
328	tRRD_ps = 6000
329	tRC_ps = 49125
330	refresh_rate_ps = 7800000
331	tIS_ps = 0
332	tIH_ps = 0
333	tDS_ps = 0
334	tDH_ps = 0
335	tRTP_ps = 7500
336	tDQSQ_max_ps = 0
337	tQHS_ps = 0
338	FSL DDR>edit c0 opts ECC_mode 0
339	FSL DDR>edit c0 regs cs0_bnds 0x000000FF
340	FSL DDR>go
341	2 GiB left unmapped
342	4 GiB (DDR3, 64-bit, CL=9, ECC off)
343	       DDR Chip-Select Interleaving Mode: CS0+CS1
344	Testing 0x00000000 - 0x7fffffff
345	Testing 0x80000000 - 0xffffffff
346	Remap DDR 2 GiB left unmapped
347
348	POST memory PASSED
349	Flash: 128 MiB
350	L2:    128 KB enabled
351	Corenet Platform Cache: 1024 KB enabled
352	SERDES: timeout resetting bank 3
353	SRIO1: disabled
354	SRIO2: disabled
355	MMC:  FSL_ESDHC: 0
356	EEPROM: Invalid ID (ff ff ff ff)
357	PCIe1: disabled
358	PCIe2: Root Complex, x1, regs @ 0xfe201000
359	  01:00.0     - 8086:10d3 - Network controller
360	PCIe2: Bus 00 - 01
361	PCIe3: disabled
362	In:    serial
363	Out:   serial
364	Err:   serial
365	Net:   Initializing Fman
366	Fman1: Uploading microcode version 101.8.0
367	e1000: 00:1b:21:81:d2:e0
368	FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME]
369	Warning: e1000#0 MAC addresses don't match:
370	Address in SROM is         00:1b:21:81:d2:e0
371	Address in environment is  00:e0:0c:00:ea:05
372
373	Hit any key to stop autoboot:  0
374	=>
375