1Table of interleaving 2-4 controllers 2===================================== 3 +--------------+-----------------------------------------------------------+ 4 |Configuration | Memory Controller | 5 | | 1 2 3 4 | 6 |--------------+--------------+--------------+-----------------------------+ 7 | Two memory | Not Intlv'ed | Not Intlv'ed | | 8 | complexes +--------------+--------------+ | 9 | | 2-way Intlv'ed | | 10 |--------------+--------------+--------------+--------------+ | 11 | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | | 12 | Three memory +--------------+--------------+--------------+ | 13 | complexes | 2-way Intlv'ed | Not Intlv'ed | | 14 | +-----------------------------+--------------+ | 15 | | 3-way Intlv'ed | | 16 +--------------+--------------+--------------+--------------+--------------+ 17 | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | 18 | Four memory +--------------+--------------+--------------+--------------+ 19 | complexes | 2-way Intlv'ed | 2-way Intlv'ed | 20 | +-----------------------------+-----------------------------+ 21 | | 4-way Intlv'ed | 22 +--------------+-----------------------------------------------------------+ 23 24 25Table of 2-way interleaving modes supported in cpu/8xxx/ddr/ 26====================================================== 27 +-------------+---------------------------------------------------------+ 28 | | Rank Interleaving | 29 | +--------+-----------+-----------+------------+-----------+ 30 |Memory | | | | 2x2 | 4x1 | 31 |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ | 32 |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} | 33 +-------------+--------+-----------+-----------+------------+-----------+ 34 |None | Yes | Yes | Yes | Yes | Yes | 35 +-------------+--------+-----------+-----------+------------+-----------+ 36 |Cacheline | Yes | Yes | No | No, Only(*)| Yes | 37 | |CS0 Only| | | {CS0+CS1} | | 38 +-------------+--------+-----------+-----------+------------+-----------+ 39 |Page | Yes | Yes | No | No, Only(*)| Yes | 40 | |CS0 Only| | | {CS0+CS1} | | 41 +-------------+--------+-----------+-----------+------------+-----------+ 42 |Bank | Yes | Yes | No | No, Only(*)| Yes | 43 | |CS0 Only| | | {CS0+CS1} | | 44 +-------------+--------+-----------+-----------+------------+-----------+ 45 |Superbank | No | Yes | No | No, Only(*)| Yes | 46 | | | | | {CS0+CS1} | | 47 +-------------+--------+-----------+-----------+------------+-----------+ 48 (*) Although the hardware can be configured with memory controller 49 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1} 50 from each controller. {CS2+CS3} on each controller are only rank 51 interleaved on that controller. 52 53 For memory controller interleaving, identical DIMMs are suggested. Software 54 doesn't check the size or organization of interleaved DIMMs. 55 56The ways to configure the ddr interleaving mode 57============================================== 581. In board header file(e.g.MPC8572DS.h), add default interleaving setting 59 under "CONFIG_EXTRA_ENV_SETTINGS", like: 60 #define CONFIG_EXTRA_ENV_SETTINGS \ 61 "hwconfig=fsl_ddr:ctlr_intlv=bank" \ 62 ...... 63 642. Run u-boot "setenv" command to configure the memory interleaving mode. 65 Either numerical or string value is accepted. 66 67 # disable memory controller interleaving 68 setenv hwconfig "fsl_ddr:ctlr_intlv=null" 69 70 # cacheline interleaving 71 setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline" 72 73 # page interleaving 74 setenv hwconfig "fsl_ddr:ctlr_intlv=page" 75 76 # bank interleaving 77 setenv hwconfig "fsl_ddr:ctlr_intlv=bank" 78 79 # superbank 80 setenv hwconfig "fsl_ddr:ctlr_intlv=superbank" 81 82 # 1KB 3-way interleaving 83 setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB" 84 85 # 4KB 3-way interleaving 86 setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB" 87 88 # 8KB 3-way interleaving 89 setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB" 90 91 # disable bank (chip-select) interleaving 92 setenv hwconfig "fsl_ddr:bank_intlv=null" 93 94 # bank(chip-select) interleaving cs0+cs1 95 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1" 96 97 # bank(chip-select) interleaving cs2+cs3 98 setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3" 99 100 # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2) 101 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3" 102 103 # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) 104 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" 105 106Memory controller address hashing 107================================== 108If the DDR controller supports address hashing, it can be enabled by hwconfig. 109 110Syntax is: 111hwconfig=fsl_ddr:addr_hash=true 112 113Memory controller ECC on/off 114============================ 115If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC, 116ECC can be turned on/off by hwconfig. 117 118Syntax is 119hwconfig=fsl_ddr:ecc=off 120 121Memory testing options for mpc85xx 122================================== 1231. Memory test can be done once U-boot prompt comes up using mtest, or 1242. Memory test can be done with Power-On-Self-Test function, activated at 125 compile time. 126 127 In order to enable the POST memory test, CONFIG_POST needs to be 128 defined in board configuraiton header file. By default, POST memory test 129 performs a fast test. A slow test can be enabled by changing the flag at 130 compiling time. To test memory bigger than 2GB, 36BIT support is needed. 131 Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB 132 window to physical address so that all physical memory can be tested. 133 134Combination of hwconfig 135======================= 136Hwconfig can be combined with multiple parameters, for example, on a supported 137platform 138 139hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on 140 141Table for dynamic ODT for DDR3 142============================== 143For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may 144be needed, depending on the configuration. The numbers in the following tables are 145in Ohms. 146 147* denotes dynamic ODT 148 149Two slots system 150+-----------------------+----------+---------------+-----------------------------+-----------------------------+ 151| Configuration | |DRAM controller| Slot 1 | Slot 2 | 152+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+ 153| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 | 154+ Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+ 155| | | | | | Write | Read | Write | Read | Write | Read | Write | Read | 156+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 157| | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 | 158| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 159| | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off | 160+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 161| | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | | 162| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 163| | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | | 164+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 165| | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 | 166|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 167| | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off | 168+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 169| | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | | 170|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 171| | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | | 172+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 173| Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | | 174+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 175| Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off | 176+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 177|Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | | 178+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 179| Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | | 180+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 181 182Single slot system 183+-------------+------------+---------------+-----------------------------+-----------------------------+ 184| | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 | 185|Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+ 186| | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read | 187+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 188| | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off | 189| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 190| | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off | 191| Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 192| | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off | 193| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 194| | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off | 195+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 196| | R1 | off | 75 | 40 | off | off | off | 197| Dual Rank |------------+-------+-------+-------+------+-------+------+ 198| | R2 | off | 75 | 40 | off | off | off | 199+-------------+------------+-------+-------+-------+------+-------+------+ 200| Single Rank | R1 | off | 75 | 40 | off | 201+-------------+------------+-------+-------+-------+------+ 202 203Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf 204 http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf 205 206 207Table for ODT for DDR2 208====================== 209Two slots system 210+-----------------------+----------+---------------+-----------------------------+-----------------------------+ 211| Configuration | |DRAM controller| Slot 1 | Slot 2 | 212+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+ 213| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 | 214+ Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+ 215| | | | | | Write | Read | Write | Read | Write | Read | Write | Read | 216+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 217| | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | off | off | 218| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 219| | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | off | off | 220+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 221| | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | | | 222| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 223| | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | | | 224+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 225| | | Slot 1 | off | 150 | off | off | | | 75 | 75 | off | off | 226|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 227| | | Slot 2 | off | 150 | 75 | 75 | | | off | off | off | off | 228+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 229| | | Slot 1 | off | 150 | off | off | | | 75 | 75 | | | 230|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 231| | | Slot 2 | off | 150 | 75 | 75 | | | off | off | | | 232+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 233| Dual Rank | Empty | Slot 1 | off | 75 | 150 | off | off | off | | | | | 234+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 235| Empty | Dual Rank | Slot 2 | off | 75 | | | | | 150 | off | off | off | 236+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 237|Single Rank| Empty | Slot 1 | off | 75 | 150 | off | | | | | | | 238+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 239| Empty |Single Rank| Slot 2 | off | 75 | | | | | 150 | off | | | 240+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 241 242Single slot system 243+-------------+------------+---------------+-----------------------------+ 244| | |DRAM controller| Rank 1 | Rank 2 | 245|Configuration| Write/Read |-------+-------+-------+------+-------+------+ 246| | | Write | Read | Write | Read | Write | Read | 247+-------------+------------+-------+-------+-------+------+-------+------+ 248| | R1 | off | 75 | 150 | off | off | off | 249| Dual Rank |------------+-------+-------+-------+------+-------+------+ 250| | R2 | off | 75 | 150 | off | off | off | 251+-------------+------------+-------+-------+-------+------+-------+------+ 252| Single Rank | R1 | off | 75 | 150 | off | 253+-------------+------------+-------+-------+-------+------+ 254 255Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf 256 257 258Interactive DDR debugging 259=========================== 260 261For DDR parameter tuning up and debugging, the interactive DDR debugging can 262be activated by saving an environment variable "ddr_interactive". The value 263doesn't matter. Once activated, U-boot prompts "FSL DDR>" before enabling DDR 264controller. The available commands can be seen by typing "help". 265 266The example flow of using interactive debugging is 267type command "compute" to calculate the parameters from the default 268type command "print" with arguments to show SPD, options, registers 269type command "edit" with arguments to change any if desired 270type command "go" to continue calculation and enable DDR controller 271type command "reset" to reset the board 272type command "recompute" to reload SPD and start over 273 274Note, check "next_step" to show the flow. For example, after edit opts, the 275next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is 276STEP_PROGRAM_REGS. Upon issuing command "go", DDR controller will be enabled 277with current setting without further calculation. 278 279The detail syntax for each commands are 280 281print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs] 282 c<n> - the controller number, eg. c0, c1 283 d<n> - the DIMM number, eg. d0, d1 284 spd - print SPD data 285 dimmparms - DIMM parameters, calculated from SPD 286 commonparms - lowest common parameters for all DIMMs 287 opts - options 288 addresses - address assignment (not implemented yet) 289 regs - controller registers 290 291edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value> 292 c<n> - the controller number, eg. c0, c1 293 d<n> - the DIMM number, eg. d0, d1 294 spd - print SPD data 295 dimmparms - DIMM parameters, calculated from SPD 296 commonparms - lowest common parameters for all DIMMs 297 opts - options 298 addresses - address assignment (not implemented yet) 299 regs - controller registers 300 <element> - name of the modified element 301 byte number if the object is SPD 302 <value> - decimal or heximal (prefixed with 0x) numbers 303 304reset 305 no arguement - reset the board 306 307recompute 308 no argument - reload SPD and start over 309 310compute 311 no argument - recompute from current next_step 312 313next_step 314 no argument - show current next_step 315 316help 317 no argument - print a list of all commands 318 319go 320 no argument - program memory controller(s) and continue with U-boot 321 322Examples of debugging flow 323 324 FSL DDR>compute 325 Detected UDIMM UG51U6400N8SU-ACF 326 SL DDR>print 327 print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs] 328 FSL DDR>print dimmparms 329 DIMM parameters: Controller=0 DIMM=0 330 DIMM organization parameters: 331 module part name = UG51U6400N8SU-ACF 332 rank_density = 2147483648 bytes (2048 megabytes) 333 capacity = 4294967296 bytes (4096 megabytes) 334 burst_lengths_bitmask = 0C 335 base_addresss = 0 (00000000 00000000) 336 n_ranks = 2 337 data_width = 64 338 primary_sdram_width = 64 339 ec_sdram_width = 0 340 registered_dimm = 0 341 n_row_addr = 15 342 n_col_addr = 10 343 edc_config = 0 344 n_banks_per_sdram_device = 8 345 tCKmin_X_ps = 1500 346 tCKmin_X_minus_1_ps = 0 347 tCKmin_X_minus_2_ps = 0 348 tCKmax_ps = 0 349 caslat_X = 960 350 tAA_ps = 13125 351 caslat_X_minus_1 = 0 352 caslat_X_minus_2 = 0 353 caslat_lowest_derated = 0 354 tRCD_ps = 13125 355 tRP_ps = 13125 356 tRAS_ps = 36000 357 tWR_ps = 15000 358 tWTR_ps = 7500 359 tRFC_ps = 160000 360 tRRD_ps = 6000 361 tRC_ps = 49125 362 refresh_rate_ps = 7800000 363 tIS_ps = 0 364 tIH_ps = 0 365 tDS_ps = 0 366 tDH_ps = 0 367 tRTP_ps = 7500 368 tDQSQ_max_ps = 0 369 tQHS_ps = 0 370 FSL DDR>edit c0 opts ECC_mode 0 371 FSL DDR>edit c0 regs cs0_bnds 0x000000FF 372 FSL DDR>go 373 2 GiB left unmapped 374 4 GiB (DDR3, 64-bit, CL=9, ECC off) 375 DDR Chip-Select Interleaving Mode: CS0+CS1 376 Testing 0x00000000 - 0x7fffffff 377 Testing 0x80000000 - 0xffffffff 378 Remap DDR 2 GiB left unmapped 379 380 POST memory PASSED 381 Flash: 128 MiB 382 L2: 128 KB enabled 383 Corenet Platform Cache: 1024 KB enabled 384 SERDES: timeout resetting bank 3 385 SRIO1: disabled 386 SRIO2: disabled 387 MMC: FSL_ESDHC: 0 388 EEPROM: Invalid ID (ff ff ff ff) 389 PCIe1: disabled 390 PCIe2: Root Complex, x1, regs @ 0xfe201000 391 01:00.0 - 8086:10d3 - Network controller 392 PCIe2: Bus 00 - 01 393 PCIe3: disabled 394 In: serial 395 Out: serial 396 Err: serial 397 Net: Initializing Fman 398 Fman1: Uploading microcode version 101.8.0 399 e1000: 00:1b:21:81:d2:e0 400 FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME] 401 Warning: e1000#0 MAC addresses don't match: 402 Address in SROM is 00:1b:21:81:d2:e0 403 Address in environment is 00:e0:0c:00:ea:05 404 405 Hit any key to stop autoboot: 0 406 => 407