1*c9ffd839SHaiying Wang 2*c9ffd839SHaiying WangTable of interleaving modes supported in cpu/8xxx/ddr/ 3*c9ffd839SHaiying Wang====================================================== 4*c9ffd839SHaiying Wang +-------------+---------------------------------------------------------+ 5*c9ffd839SHaiying Wang | | Rank Interleaving | 6*c9ffd839SHaiying Wang | +--------+-----------+-----------+------------+-----------+ 7*c9ffd839SHaiying Wang |Memory | | | | 2x2 | 4x1 | 8*c9ffd839SHaiying Wang |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ | 9*c9ffd839SHaiying Wang |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} | 10*c9ffd839SHaiying Wang +-------------+--------+-----------+-----------+------------+-----------+ 11*c9ffd839SHaiying Wang |None | Yes | Yes | Yes | Yes | Yes | 12*c9ffd839SHaiying Wang +-------------+--------+-----------+-----------+------------+-----------+ 13*c9ffd839SHaiying Wang |Cacheline | Yes | Yes | No | No, Only(*)| Yes | 14*c9ffd839SHaiying Wang | |CS0 Only| | | {CS0+CS1} | | 15*c9ffd839SHaiying Wang +-------------+--------+-----------+-----------+------------+-----------+ 16*c9ffd839SHaiying Wang |Page | Yes | Yes | No | No, Only(*)| Yes | 17*c9ffd839SHaiying Wang | |CS0 Only| | | {CS0+CS1} | | 18*c9ffd839SHaiying Wang +-------------+--------+-----------+-----------+------------+-----------+ 19*c9ffd839SHaiying Wang |Bank | Yes | Yes | No | No, Only(*)| Yes | 20*c9ffd839SHaiying Wang | |CS0 Only| | | {CS0+CS1} | | 21*c9ffd839SHaiying Wang +-------------+--------+-----------+-----------+------------+-----------+ 22*c9ffd839SHaiying Wang |Superbank | No | Yes | No | No, Only(*)| Yes | 23*c9ffd839SHaiying Wang | | | | | {CS0+CS1} | | 24*c9ffd839SHaiying Wang +-------------+--------+-----------+-----------+------------+-----------+ 25*c9ffd839SHaiying Wang (*) Although the hardware can be configured with memory controller 26*c9ffd839SHaiying Wang interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1} 27*c9ffd839SHaiying Wang from each controller. {CS2+CS3} on each controller are only rank 28*c9ffd839SHaiying Wang interleaved on that controller. 29*c9ffd839SHaiying Wang 30*c9ffd839SHaiying WangThe ways to configure the ddr interleaving mode 31*c9ffd839SHaiying Wang============================================== 32*c9ffd839SHaiying Wang1. In board header file(e.g.MPC8572DS.h), add default interleaving setting 33*c9ffd839SHaiying Wang under "CONFIG_EXTRA_ENV_SETTINGS", like: 34*c9ffd839SHaiying Wang #define CONFIG_EXTRA_ENV_SETTINGS \ 35*c9ffd839SHaiying Wang "memctl_intlv_ctl=2\0" \ 36*c9ffd839SHaiying Wang ...... 37*c9ffd839SHaiying Wang 38*c9ffd839SHaiying Wang2. Run u-boot "setenv" command to configure the memory interleaving mode. 39*c9ffd839SHaiying Wang Either numerical or string value is accepted. 40*c9ffd839SHaiying Wang 41*c9ffd839SHaiying Wang # disable memory controller interleaving 42*c9ffd839SHaiying Wang setenv memctl_intlv_ctl 43*c9ffd839SHaiying Wang 44*c9ffd839SHaiying Wang # cacheline interleaving 45*c9ffd839SHaiying Wang setenv memctl_intlv_ctl 0 or setenv memctl_intlv_ctl cacheline 46*c9ffd839SHaiying Wang 47*c9ffd839SHaiying Wang # page interleaving 48*c9ffd839SHaiying Wang setenv memctl_intlv_ctl 1 or setenv memctl_intlv_ctl page 49*c9ffd839SHaiying Wang 50*c9ffd839SHaiying Wang # bank interleaving 51*c9ffd839SHaiying Wang setenv memctl_intlv_ctl 2 or setenv memctl_intlv_ctl bank 52*c9ffd839SHaiying Wang 53*c9ffd839SHaiying Wang # superbank 54*c9ffd839SHaiying Wang setenv memctl_intlv_ctl 3 or setenv memctl_intlv_ctl superbank 55*c9ffd839SHaiying Wang 56*c9ffd839SHaiying Wang # disable bank (chip-select) interleaving 57*c9ffd839SHaiying Wang setenv ba_intlv_ctl 58*c9ffd839SHaiying Wang 59*c9ffd839SHaiying Wang # bank(chip-select) interleaving cs0+cs1 60*c9ffd839SHaiying Wang setenv ba_intlv_ctl 0x40 or setenv ba_intlv_ctl cs0_cs1 61*c9ffd839SHaiying Wang 62*c9ffd839SHaiying Wang # bank(chip-select) interleaving cs2+cs3 63*c9ffd839SHaiying Wang setenv ba_intlv_ctl 0x20 or setenv ba_intlv_ctl cs2_cs3 64*c9ffd839SHaiying Wang 65*c9ffd839SHaiying Wang # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2) 66*c9ffd839SHaiying Wang setenv ba_intlv_ctl 0x60 or setenv ba_intlv_ctl cs0_cs1_and_cs2_cs3 67*c9ffd839SHaiying Wang 68*c9ffd839SHaiying Wang # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) 69*c9ffd839SHaiying Wang setenv ba_intlv_ctl 0x04 or setenv ba_intlv_ctl cs0_cs1_cs2_cs3 70