1c9ffd839SHaiying Wang 2c9ffd839SHaiying WangTable of interleaving modes supported in cpu/8xxx/ddr/ 3c9ffd839SHaiying Wang====================================================== 4c9ffd839SHaiying Wang +-------------+---------------------------------------------------------+ 5c9ffd839SHaiying Wang | | Rank Interleaving | 6c9ffd839SHaiying Wang | +--------+-----------+-----------+------------+-----------+ 7c9ffd839SHaiying Wang |Memory | | | | 2x2 | 4x1 | 8c9ffd839SHaiying Wang |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ | 9c9ffd839SHaiying Wang |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} | 10c9ffd839SHaiying Wang +-------------+--------+-----------+-----------+------------+-----------+ 11c9ffd839SHaiying Wang |None | Yes | Yes | Yes | Yes | Yes | 12c9ffd839SHaiying Wang +-------------+--------+-----------+-----------+------------+-----------+ 13c9ffd839SHaiying Wang |Cacheline | Yes | Yes | No | No, Only(*)| Yes | 14c9ffd839SHaiying Wang | |CS0 Only| | | {CS0+CS1} | | 15c9ffd839SHaiying Wang +-------------+--------+-----------+-----------+------------+-----------+ 16c9ffd839SHaiying Wang |Page | Yes | Yes | No | No, Only(*)| Yes | 17c9ffd839SHaiying Wang | |CS0 Only| | | {CS0+CS1} | | 18c9ffd839SHaiying Wang +-------------+--------+-----------+-----------+------------+-----------+ 19c9ffd839SHaiying Wang |Bank | Yes | Yes | No | No, Only(*)| Yes | 20c9ffd839SHaiying Wang | |CS0 Only| | | {CS0+CS1} | | 21c9ffd839SHaiying Wang +-------------+--------+-----------+-----------+------------+-----------+ 22c9ffd839SHaiying Wang |Superbank | No | Yes | No | No, Only(*)| Yes | 23c9ffd839SHaiying Wang | | | | | {CS0+CS1} | | 24c9ffd839SHaiying Wang +-------------+--------+-----------+-----------+------------+-----------+ 25c9ffd839SHaiying Wang (*) Although the hardware can be configured with memory controller 26c9ffd839SHaiying Wang interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1} 27c9ffd839SHaiying Wang from each controller. {CS2+CS3} on each controller are only rank 28c9ffd839SHaiying Wang interleaved on that controller. 29c9ffd839SHaiying Wang 30*076bff8fSyork For memory controller interleaving, identical DIMMs are suggested. Software 31*076bff8fSyork doesn't check the size or organization of interleaved DIMMs. 32*076bff8fSyork 33c9ffd839SHaiying WangThe ways to configure the ddr interleaving mode 34c9ffd839SHaiying Wang============================================== 35c9ffd839SHaiying Wang1. In board header file(e.g.MPC8572DS.h), add default interleaving setting 36c9ffd839SHaiying Wang under "CONFIG_EXTRA_ENV_SETTINGS", like: 37c9ffd839SHaiying Wang #define CONFIG_EXTRA_ENV_SETTINGS \ 3879e4e648SKumar Gala "hwconfig=fsl_ddr:ctlr_intlv=bank" \ 39c9ffd839SHaiying Wang ...... 40c9ffd839SHaiying Wang 41c9ffd839SHaiying Wang2. Run u-boot "setenv" command to configure the memory interleaving mode. 42c9ffd839SHaiying Wang Either numerical or string value is accepted. 43c9ffd839SHaiying Wang 44c9ffd839SHaiying Wang # disable memory controller interleaving 4579e4e648SKumar Gala setenv hwconfig "fsl_ddr:ctlr_intlv=null" 46c9ffd839SHaiying Wang 47c9ffd839SHaiying Wang # cacheline interleaving 4879e4e648SKumar Gala setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline" 49c9ffd839SHaiying Wang 50c9ffd839SHaiying Wang # page interleaving 5179e4e648SKumar Gala setenv hwconfig "fsl_ddr:ctlr_intlv=page" 52c9ffd839SHaiying Wang 53c9ffd839SHaiying Wang # bank interleaving 5479e4e648SKumar Gala setenv hwconfig "fsl_ddr:ctlr_intlv=bank" 55c9ffd839SHaiying Wang 56c9ffd839SHaiying Wang # superbank 5779e4e648SKumar Gala setenv hwconfig "fsl_ddr:ctlr_intlv=superbank" 58c9ffd839SHaiying Wang 59c9ffd839SHaiying Wang # disable bank (chip-select) interleaving 6079e4e648SKumar Gala setenv hwconfig "fsl_ddr:bank_intlv=null" 61c9ffd839SHaiying Wang 62c9ffd839SHaiying Wang # bank(chip-select) interleaving cs0+cs1 6379e4e648SKumar Gala setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1" 64c9ffd839SHaiying Wang 65c9ffd839SHaiying Wang # bank(chip-select) interleaving cs2+cs3 6679e4e648SKumar Gala setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3" 67c9ffd839SHaiying Wang 68c9ffd839SHaiying Wang # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2) 6979e4e648SKumar Gala setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3" 70c9ffd839SHaiying Wang 71c9ffd839SHaiying Wang # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) 7279e4e648SKumar Gala setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" 7379e4e648SKumar Gala 7479e4e648SKumar Gala The above memory controller interleaving and bank interleaving can be mixed. The syntax is 7579e4e648SKumar Gala setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1" 76