1*cba4b180SAneesh VDisabling I-cache: 2*cba4b180SAneesh V- Set CONFIG_SYS_ICACHE_OFF 3*cba4b180SAneesh V 4*cba4b180SAneesh VDisabling D-cache: 5*cba4b180SAneesh V- Set CONFIG_SYS_DCACHE_OFF 6*cba4b180SAneesh V 7*cba4b180SAneesh VEnabling I-cache: 8*cba4b180SAneesh V- Make sure CONFIG_SYS_ICACHE_OFF is not set and call icache_enable(). 9*cba4b180SAneesh V 10*cba4b180SAneesh VEnabling D-cache: 11*cba4b180SAneesh V- Make sure CONFIG_SYS_DCACHE_OFF is not set and call dcache_enable(). 12*cba4b180SAneesh V 13*cba4b180SAneesh VEnabling Caches at System Startup: 14*cba4b180SAneesh V- Implement enable_caches() for your platform and enable the I-cache and 15*cba4b180SAneesh V D-cache from this function. This function is called immediately 16*cba4b180SAneesh V after relocation. 17*cba4b180SAneesh V 18*cba4b180SAneesh VGuidelines for Working with D-cache: 19*cba4b180SAneesh V 20*cba4b180SAneesh VMemory to Peripheral DMA: 21*cba4b180SAneesh V- Flush the buffer after the MPU writes the data and before the DMA is 22*cba4b180SAneesh V initiated. 23*cba4b180SAneesh V 24*cba4b180SAneesh VPeripheral to Memory DMA: 25*cba4b180SAneesh V- Invalidate the buffer before starting the DMA. In case there are any dirty 26*cba4b180SAneesh V lines from the DMA buffer in the cache, subsequent cache-line replacements 27*cba4b180SAneesh V may corrupt the buffer in memory while the DMA is still going on. Cache-line 28*cba4b180SAneesh V replacement can happen if the CPU tries to bring some other memory locations 29*cba4b180SAneesh V into the cache while the DMA is going on. 30*cba4b180SAneesh V- Invalidate the buffer after the DMA is complete and before the MPU reads 31*cba4b180SAneesh V it. This may be needed in addition to the invalidation before the DMA 32*cba4b180SAneesh V mentioned above, because in some processors memory contents can spontaneously 33*cba4b180SAneesh V come to the cache due to speculative memory access by the CPU. If this 34*cba4b180SAneesh V happens with the DMA buffer while DMA is going on we have a coherency problem. 35*cba4b180SAneesh V 36*cba4b180SAneesh VBuffer Requirements: 37*cba4b180SAneesh V- Any buffer that is invalidated(that is, typically the peripheral to 38*cba4b180SAneesh V memory DMA buffer) should be aligned to cache-line boundary both at 39*cba4b180SAneesh V at the beginning and at the end of the buffer. 40*cba4b180SAneesh V- If the buffer is not cache-line aligned invalidation will be restricted 41*cba4b180SAneesh V to the aligned part. That is, one cache-line at the respective boundary 42*cba4b180SAneesh V may be left out while doing invalidation. 43*cba4b180SAneesh V 44*cba4b180SAneesh VCleanup Before Linux: 45*cba4b180SAneesh V- cleanup_before_linux() should flush the D-cache, invalidate I-cache, and 46*cba4b180SAneesh V disable MMU and caches. 47*cba4b180SAneesh V- The following sequence is advisable while disabling d-cache: 48*cba4b180SAneesh V 1. disable_dcache() - flushes and disables d-cache 49*cba4b180SAneesh V 2. invalidate_dcache_all() - invalid any entry that came to the cache 50*cba4b180SAneesh V in the short period after the cache was flushed but before the 51*cba4b180SAneesh V cache got disabled. 52