1I2C Edge Conditions: 2==================== 3 4 I2C devices may be left in a write state if a read was occuring 5 and the CPU was reset. This may result in EEPROM data corruption. 6 7 The edge condition is as follows: 8 1) A read operation begins. 9 2) I2C controller issues a start command. 10 3) The I2C writes the device address. 11 4) The CPU is reset at this point. 12 13 Once the CPU reinitializes and the read is tried again: 14 1) The I2C controller issues a start command. 15 2) The I2C controller writes the device address. 16 3) The I2C controller writes the offset. 17 18 The EEPROM sees: 19 1) START 20 2) device address 21 3) START "this start is ignored by most EEPROMs" 22 4) device address "EEPROM interprets this as offset" 23 5) Offset in device, "EEPROM interprets this as data to write" 24 25 The device will interpret this sequence as a WRITE command and 26 write rubbish into itself, i.e. the "offset" will be interpreted 27 as data to be written in location "device address". 28 29Notes 30----- 31!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A AMCC 4xx BUG!!! 32 33This reset edge condition could possibly be present in every I2C 34controller and device available. For boards where a I2C bus reset 35function can be implemented a i2c_init_board() function should be 36provided and enabled by #define'ing CFG_I2C_INIT_BOARD in your 37board's config file. Note that this is NOT necessary when using the 38bit-banging I2C driver (common/soft_i2c.c) as this already includes 39the I2C bus reset sequence. 40 41 42Many thanks to Bill Hunter for finding this serious BUG. 43email to: <williamhunter@attbi.com> 44 45Erik Theisen <etheisen@mindspring.com> 46Tue, 5 Mar 2002 23:02:19 -0500 (Wed 05:02 MET) 47