xref: /openbmc/u-boot/doc/I2C_Edge_Conditions (revision 6fcc18e0a92788073c9c869ed2ff86a2f44bdce9)
1*6fcc18e0SwdenkI2C Edge Conditions:
2*6fcc18e0Swdenk====================
3*6fcc18e0Swdenk
4*6fcc18e0Swdenk    I2C devices may be left in a write state if a read was occuring
5*6fcc18e0Swdenk    and the CPU was reset. This may result in EEPROM data corruption.
6*6fcc18e0Swdenk
7*6fcc18e0Swdenk    The edge condition is as follows:
8*6fcc18e0Swdenk	1) A read operation begins.
9*6fcc18e0Swdenk	2) I2C controller issues a start command.
10*6fcc18e0Swdenk	3) The I2C writes the device address.
11*6fcc18e0Swdenk	4) The CPU is reset at this point.
12*6fcc18e0Swdenk
13*6fcc18e0Swdenk    Once the CPU reinitializes and the read is tried again:
14*6fcc18e0Swdenk	1) The I2C controller issues a start command.
15*6fcc18e0Swdenk	2) The I2C controller writes the device address.
16*6fcc18e0Swdenk	3) The I2C controller writes the offset.
17*6fcc18e0Swdenk
18*6fcc18e0Swdenk    The EEPROM sees:
19*6fcc18e0Swdenk	1) START
20*6fcc18e0Swdenk	2) device address
21*6fcc18e0Swdenk	3) START "this start is ignored by most EEPROMs"
22*6fcc18e0Swdenk	4) device address "EEPROM interprets this as offset"
23*6fcc18e0Swdenk	5) Offset in device, "EEPROM interprets this as data to write"
24*6fcc18e0Swdenk
25*6fcc18e0Swdenk    The device will interpret this sequence as a WRITE command and
26*6fcc18e0Swdenk    write rubbish into itself, i.e. the "offset" will be interpreted
27*6fcc18e0Swdenk    as data to be written in location "device address".
28*6fcc18e0Swdenk
29*6fcc18e0SwdenkNotes
30*6fcc18e0Swdenk-----
31*6fcc18e0Swdenk!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A IBM 4xx BUG!!!
32*6fcc18e0Swdenk
33*6fcc18e0SwdenkThis reset edge condition could possibly be present in every I2C
34*6fcc18e0Swdenkcontroller and device available. We should probably have a bus reset
35*6fcc18e0Swdenkfunction for all our target CPUs.
36*6fcc18e0Swdenk
37*6fcc18e0SwdenkMany thanks to Bill Hunter for finding this serious BUG.
38*6fcc18e0Swdenkemail to: <williamhunter@attbi.com>
39*6fcc18e0Swdenk
40*6fcc18e0SwdenkErik Theisen <etheisen@mindspring.com>
41*6fcc18e0SwdenkTue, 5 Mar 2002 23:02:19 -0500 (Wed 05:02 MET)
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