16fcc18e0SwdenkI2C Edge Conditions: 26fcc18e0Swdenk==================== 36fcc18e0Swdenk 46fcc18e0Swdenk I2C devices may be left in a write state if a read was occuring 56fcc18e0Swdenk and the CPU was reset. This may result in EEPROM data corruption. 66fcc18e0Swdenk 76fcc18e0Swdenk The edge condition is as follows: 86fcc18e0Swdenk 1) A read operation begins. 96fcc18e0Swdenk 2) I2C controller issues a start command. 106fcc18e0Swdenk 3) The I2C writes the device address. 116fcc18e0Swdenk 4) The CPU is reset at this point. 126fcc18e0Swdenk 136fcc18e0Swdenk Once the CPU reinitializes and the read is tried again: 146fcc18e0Swdenk 1) The I2C controller issues a start command. 156fcc18e0Swdenk 2) The I2C controller writes the device address. 166fcc18e0Swdenk 3) The I2C controller writes the offset. 176fcc18e0Swdenk 186fcc18e0Swdenk The EEPROM sees: 196fcc18e0Swdenk 1) START 206fcc18e0Swdenk 2) device address 216fcc18e0Swdenk 3) START "this start is ignored by most EEPROMs" 226fcc18e0Swdenk 4) device address "EEPROM interprets this as offset" 236fcc18e0Swdenk 5) Offset in device, "EEPROM interprets this as data to write" 246fcc18e0Swdenk 256fcc18e0Swdenk The device will interpret this sequence as a WRITE command and 266fcc18e0Swdenk write rubbish into itself, i.e. the "offset" will be interpreted 276fcc18e0Swdenk as data to be written in location "device address". 286fcc18e0Swdenk 296fcc18e0SwdenkNotes 306fcc18e0Swdenk----- 316fcc18e0Swdenk!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A IBM 4xx BUG!!! 326fcc18e0Swdenk 336fcc18e0SwdenkThis reset edge condition could possibly be present in every I2C 34*3e38691eSwdenkcontroller and device available. For boards where a I2C bus reset 35*3e38691eSwdenkfunction can be implemented a i2c_init_board() function should be 36*3e38691eSwdenkprovided and enabled by #define'ing CFG_I2C_INIT_BOARD in your 37*3e38691eSwdenkboard's config file. Note that this is NOT necessary when using the 38*3e38691eSwdenkbit-banging I2C driver (common/soft_i2c.c) as this already includes 39*3e38691eSwdenkthe I2C bus reset sequence. 40*3e38691eSwdenk 416fcc18e0Swdenk 426fcc18e0SwdenkMany thanks to Bill Hunter for finding this serious BUG. 436fcc18e0Swdenkemail to: <williamhunter@attbi.com> 446fcc18e0Swdenk 456fcc18e0SwdenkErik Theisen <etheisen@mindspring.com> 466fcc18e0SwdenkTue, 5 Mar 2002 23:02:19 -0500 (Wed 05:02 MET) 47