1ae9996c8SStefan RoeseCONFIG_ARM=y 2ae9996c8SStefan RoeseCONFIG_ARCH_SOCFPGA=y 3ae9996c8SStefan RoeseCONFIG_SYS_MALLOC_F_LEN=0x2000 4ae9996c8SStefan RoeseCONFIG_SPL_DM=y 5ae9996c8SStefan RoeseCONFIG_DM_GPIO=y 6ae9996c8SStefan RoeseCONFIG_TARGET_SOCFPGA_SR1500=y 74edb9458SSimon GlassCONFIG_SPL_STACK_R_ADDR=0x00800000 8ae9996c8SStefan RoeseCONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" 9ae9996c8SStefan RoeseCONFIG_SPL=y 10ae9996c8SStefan RoeseCONFIG_SPL_STACK_R=y 1173223f0eSSimon GlassCONFIG_FIT=y 12*adad96e6STom RiniCONFIG_HUSH_PARSER=y 13ae9996c8SStefan Roese# CONFIG_CMD_IMLS is not set 14ae9996c8SStefan Roese# CONFIG_CMD_FLASH is not set 154edb9458SSimon GlassCONFIG_SPL_DM_SEQ_ALIAS=y 16ae9996c8SStefan RoeseCONFIG_DWAPB_GPIO=y 174edb9458SSimon GlassCONFIG_DM_MMC=y 18ae9996c8SStefan RoeseCONFIG_SPI_FLASH=y 19*adad96e6STom RiniCONFIG_SPI_FLASH_BAR=y 2093d9fc26SStefan RoeseCONFIG_SPI_FLASH_STMICRO=y 214edb9458SSimon Glass# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set 22ae9996c8SStefan RoeseCONFIG_DM_ETH=y 23ae9996c8SStefan RoeseCONFIG_ETH_DESIGNWARE=y 24ae9996c8SStefan RoeseCONFIG_SYS_NS16550=y 2593d9fc26SStefan RoeseCONFIG_CADENCE_QSPI=y 26