1ae9996c8SStefan RoeseCONFIG_ARM=y 2ae9996c8SStefan RoeseCONFIG_ARCH_SOCFPGA=y 3ae9996c8SStefan RoeseCONFIG_SYS_MALLOC_F_LEN=0x2000 4ae9996c8SStefan RoeseCONFIG_SPL_DM=y 5ae9996c8SStefan RoeseCONFIG_DM_GPIO=y 6ae9996c8SStefan RoeseCONFIG_TARGET_SOCFPGA_SR1500=y 7*4edb9458SSimon GlassCONFIG_SPL_STACK_R_ADDR=0x00800000 8ae9996c8SStefan RoeseCONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" 9ae9996c8SStefan RoeseCONFIG_SPL=y 10ae9996c8SStefan RoeseCONFIG_SPL_STACK_R=y 11ae9996c8SStefan Roese# CONFIG_CMD_IMLS is not set 12ae9996c8SStefan Roese# CONFIG_CMD_FLASH is not set 13*4edb9458SSimon GlassCONFIG_SPL_DM_SEQ_ALIAS=y 14ae9996c8SStefan RoeseCONFIG_DWAPB_GPIO=y 15*4edb9458SSimon GlassCONFIG_DM_MMC=y 16ae9996c8SStefan RoeseCONFIG_SPI_FLASH=y 17*4edb9458SSimon Glass# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set 18ae9996c8SStefan RoeseCONFIG_DM_ETH=y 19ae9996c8SStefan RoeseCONFIG_ETH_DESIGNWARE=y 20ae9996c8SStefan RoeseCONFIG_SYS_NS16550=y 21