1*55c7a765SDinh NguyenCONFIG_ARM=y 2*55c7a765SDinh NguyenCONFIG_ARCH_SOCFPGA=y 3*55c7a765SDinh NguyenCONFIG_TARGET_SOCFPGA_CYCLONE5=y 4*55c7a765SDinh NguyenCONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y 5*55c7a765SDinh NguyenCONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc" 6*55c7a765SDinh NguyenCONFIG_SPL=y 7*55c7a765SDinh Nguyen# CONFIG_CMD_IMLS is not set 8*55c7a765SDinh Nguyen# CONFIG_CMD_FLASH is not set 9*55c7a765SDinh NguyenCONFIG_OF_CONTROL=y 10*55c7a765SDinh NguyenCONFIG_DM_ETH=y 11*55c7a765SDinh NguyenCONFIG_NETDEVICES=y 12*55c7a765SDinh NguyenCONFIG_ETH_DESIGNWARE=y 13*55c7a765SDinh NguyenCONFIG_DM_GPIO=y 14*55c7a765SDinh NguyenCONFIG_DWAPB_GPIO=y 15*55c7a765SDinh NguyenCONFIG_SPL_DM=y 16*55c7a765SDinh NguyenCONFIG_SPL_MMC_SUPPORT=y 17*55c7a765SDinh NguyenCONFIG_SPL_SIMPLE_BUS=y 18*55c7a765SDinh NguyenCONFIG_SPL_STACK_R=y 19*55c7a765SDinh NguyenCONFIG_SPL_STACK_R_ADDR=0x00800000 20*55c7a765SDinh NguyenCONFIG_SYS_MALLOC_F_LEN=0x2000 21