1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * (C) Copyright 2002-2006 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * (C) Copyright 2002 8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 9 * Marius Groeger <mgroeger@sysgo.de> 10 */ 11 12 #include <common.h> 13 #include <console.h> 14 #include <cpu.h> 15 #include <dm.h> 16 #include <environment.h> 17 #include <fdtdec.h> 18 #include <fs.h> 19 #include <i2c.h> 20 #include <initcall.h> 21 #include <malloc.h> 22 #include <mapmem.h> 23 #include <os.h> 24 #include <post.h> 25 #include <relocate.h> 26 #include <status_led.h> 27 #include <sysreset.h> 28 #include <timer.h> 29 #include <trace.h> 30 #include <video.h> 31 #include <watchdog.h> 32 #ifdef CONFIG_MACH_TYPE 33 #include <asm/mach-types.h> 34 #endif 35 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 36 #include <asm/mp.h> 37 #endif 38 #include <asm/io.h> 39 #include <asm/sections.h> 40 #include <dm/root.h> 41 #include <linux/errno.h> 42 43 /* 44 * Pointer to initial global data area 45 * 46 * Here we initialize it if needed. 47 */ 48 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 49 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 50 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 51 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR); 52 #else 53 DECLARE_GLOBAL_DATA_PTR; 54 #endif 55 56 /* 57 * TODO(sjg@chromium.org): IMO this code should be 58 * refactored to a single function, something like: 59 * 60 * void led_set_state(enum led_colour_t colour, int on); 61 */ 62 /************************************************************************ 63 * Coloured LED functionality 64 ************************************************************************ 65 * May be supplied by boards if desired 66 */ 67 __weak void coloured_LED_init(void) {} 68 __weak void red_led_on(void) {} 69 __weak void red_led_off(void) {} 70 __weak void green_led_on(void) {} 71 __weak void green_led_off(void) {} 72 __weak void yellow_led_on(void) {} 73 __weak void yellow_led_off(void) {} 74 __weak void blue_led_on(void) {} 75 __weak void blue_led_off(void) {} 76 77 /* 78 * Why is gd allocated a register? Prior to reloc it might be better to 79 * just pass it around to each function in this file? 80 * 81 * After reloc one could argue that it is hardly used and doesn't need 82 * to be in a register. Or if it is it should perhaps hold pointers to all 83 * global data for all modules, so that post-reloc we can avoid the massive 84 * literal pool we get on ARM. Or perhaps just encourage each module to use 85 * a structure... 86 */ 87 88 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 89 static int init_func_watchdog_init(void) 90 { 91 # if defined(CONFIG_HW_WATCHDOG) && \ 92 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 93 defined(CONFIG_SH) || \ 94 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 95 defined(CONFIG_IMX_WATCHDOG)) 96 hw_watchdog_init(); 97 puts(" Watchdog enabled\n"); 98 # endif 99 WATCHDOG_RESET(); 100 101 return 0; 102 } 103 104 int init_func_watchdog_reset(void) 105 { 106 WATCHDOG_RESET(); 107 108 return 0; 109 } 110 #endif /* CONFIG_WATCHDOG */ 111 112 __weak void board_add_ram_info(int use_default) 113 { 114 /* please define platform specific board_add_ram_info() */ 115 } 116 117 static int init_baud_rate(void) 118 { 119 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 120 return 0; 121 } 122 123 static int display_text_info(void) 124 { 125 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 126 ulong bss_start, bss_end, text_base; 127 128 bss_start = (ulong)&__bss_start; 129 bss_end = (ulong)&__bss_end; 130 131 #ifdef CONFIG_SYS_TEXT_BASE 132 text_base = CONFIG_SYS_TEXT_BASE; 133 #else 134 text_base = CONFIG_SYS_MONITOR_BASE; 135 #endif 136 137 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 138 text_base, bss_start, bss_end); 139 #endif 140 141 return 0; 142 } 143 144 #ifdef CONFIG_SYSRESET 145 static int print_resetinfo(void) 146 { 147 struct udevice *dev; 148 char status[256]; 149 int ret; 150 151 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev); 152 if (ret) { 153 debug("%s: No sysreset device found (error: %d)\n", 154 __func__, ret); 155 /* Not all boards have sysreset drivers available during early 156 * boot, so don't fail if one can't be found. 157 */ 158 return 0; 159 } 160 161 if (!sysreset_get_status(dev, status, sizeof(status))) 162 printf("%s", status); 163 164 return 0; 165 } 166 #endif 167 168 #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU) 169 static int print_cpuinfo(void) 170 { 171 struct udevice *dev; 172 char desc[512]; 173 int ret; 174 175 ret = uclass_first_device_err(UCLASS_CPU, &dev); 176 if (ret) { 177 debug("%s: Could not get CPU device (err = %d)\n", 178 __func__, ret); 179 return ret; 180 } 181 182 ret = cpu_get_desc(dev, desc, sizeof(desc)); 183 if (ret) { 184 debug("%s: Could not get CPU description (err = %d)\n", 185 dev->name, ret); 186 return ret; 187 } 188 189 printf("CPU: %s\n", desc); 190 191 return 0; 192 } 193 #endif 194 195 static int announce_dram_init(void) 196 { 197 puts("DRAM: "); 198 return 0; 199 } 200 201 static int show_dram_config(void) 202 { 203 unsigned long long size; 204 205 #ifdef CONFIG_NR_DRAM_BANKS 206 int i; 207 208 debug("\nRAM Configuration:\n"); 209 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 210 size += gd->bd->bi_dram[i].size; 211 debug("Bank #%d: %llx ", i, 212 (unsigned long long)(gd->bd->bi_dram[i].start)); 213 #ifdef DEBUG 214 print_size(gd->bd->bi_dram[i].size, "\n"); 215 #endif 216 } 217 debug("\nDRAM: "); 218 #else 219 size = gd->ram_size; 220 #endif 221 222 print_size(size, ""); 223 board_add_ram_info(0); 224 putc('\n'); 225 226 return 0; 227 } 228 229 __weak int dram_init_banksize(void) 230 { 231 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 232 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 233 gd->bd->bi_dram[0].size = get_effective_memsize(); 234 #endif 235 236 return 0; 237 } 238 239 #if defined(CONFIG_SYS_I2C) 240 static int init_func_i2c(void) 241 { 242 puts("I2C: "); 243 #ifdef CONFIG_SYS_I2C 244 i2c_init_all(); 245 #else 246 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 247 #endif 248 puts("ready\n"); 249 return 0; 250 } 251 #endif 252 253 #if defined(CONFIG_VID) 254 __weak int init_func_vid(void) 255 { 256 return 0; 257 } 258 #endif 259 260 #if defined(CONFIG_HARD_SPI) 261 static int init_func_spi(void) 262 { 263 puts("SPI: "); 264 puts("ready\n"); 265 return 0; 266 } 267 #endif 268 269 static int setup_mon_len(void) 270 { 271 #if defined(__ARM__) || defined(__MICROBLAZE__) 272 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 273 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 274 gd->mon_len = (ulong)&_end - (ulong)_init; 275 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 276 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 277 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV) 278 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 279 #elif defined(CONFIG_SYS_MONITOR_BASE) 280 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 281 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 282 #endif 283 return 0; 284 } 285 286 __weak int arch_cpu_init(void) 287 { 288 return 0; 289 } 290 291 __weak int mach_cpu_init(void) 292 { 293 return 0; 294 } 295 296 /* Get the top of usable RAM */ 297 __weak ulong board_get_usable_ram_top(ulong total_size) 298 { 299 #ifdef CONFIG_SYS_SDRAM_BASE 300 /* 301 * Detect whether we have so much RAM that it goes past the end of our 302 * 32-bit address space. If so, clip the usable RAM so it doesn't. 303 */ 304 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 305 /* 306 * Will wrap back to top of 32-bit space when reservations 307 * are made. 308 */ 309 return 0; 310 #endif 311 return gd->ram_top; 312 } 313 314 static int setup_dest_addr(void) 315 { 316 debug("Monitor len: %08lX\n", gd->mon_len); 317 /* 318 * Ram is setup, size stored in gd !! 319 */ 320 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 321 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 322 /* 323 * Subtract specified amount of memory to hide so that it won't 324 * get "touched" at all by U-Boot. By fixing up gd->ram_size 325 * the Linux kernel should now get passed the now "corrected" 326 * memory size and won't touch it either. This should work 327 * for arch/ppc and arch/powerpc. Only Linux board ports in 328 * arch/powerpc with bootwrapper support, that recalculate the 329 * memory size from the SDRAM controller setup will have to 330 * get fixed. 331 */ 332 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 333 #endif 334 #ifdef CONFIG_SYS_SDRAM_BASE 335 gd->ram_base = CONFIG_SYS_SDRAM_BASE; 336 #endif 337 gd->ram_top = gd->ram_base + get_effective_memsize(); 338 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 339 gd->relocaddr = gd->ram_top; 340 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 341 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 342 /* 343 * We need to make sure the location we intend to put secondary core 344 * boot code is reserved and not used by any part of u-boot 345 */ 346 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 347 gd->relocaddr = determine_mp_bootpg(NULL); 348 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 349 } 350 #endif 351 return 0; 352 } 353 354 #ifdef CONFIG_PRAM 355 /* reserve protected RAM */ 356 static int reserve_pram(void) 357 { 358 ulong reg; 359 360 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 361 gd->relocaddr -= (reg << 10); /* size is in kB */ 362 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 363 gd->relocaddr); 364 return 0; 365 } 366 #endif /* CONFIG_PRAM */ 367 368 /* Round memory pointer down to next 4 kB limit */ 369 static int reserve_round_4k(void) 370 { 371 gd->relocaddr &= ~(4096 - 1); 372 return 0; 373 } 374 375 #ifdef CONFIG_ARM 376 __weak int reserve_mmu(void) 377 { 378 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 379 /* reserve TLB table */ 380 gd->arch.tlb_size = PGTABLE_SIZE; 381 gd->relocaddr -= gd->arch.tlb_size; 382 383 /* round down to next 64 kB limit */ 384 gd->relocaddr &= ~(0x10000 - 1); 385 386 gd->arch.tlb_addr = gd->relocaddr; 387 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 388 gd->arch.tlb_addr + gd->arch.tlb_size); 389 390 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 391 /* 392 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 393 * with location within secure ram. 394 */ 395 gd->arch.tlb_allocated = gd->arch.tlb_addr; 396 #endif 397 #endif 398 399 return 0; 400 } 401 #endif 402 403 static int reserve_video(void) 404 { 405 #ifdef CONFIG_DM_VIDEO 406 ulong addr; 407 int ret; 408 409 addr = gd->relocaddr; 410 ret = video_reserve(&addr); 411 if (ret) 412 return ret; 413 gd->relocaddr = addr; 414 #elif defined(CONFIG_LCD) 415 # ifdef CONFIG_FB_ADDR 416 gd->fb_base = CONFIG_FB_ADDR; 417 # else 418 /* reserve memory for LCD display (always full pages) */ 419 gd->relocaddr = lcd_setmem(gd->relocaddr); 420 gd->fb_base = gd->relocaddr; 421 # endif /* CONFIG_FB_ADDR */ 422 #elif defined(CONFIG_VIDEO) && \ 423 (!defined(CONFIG_PPC)) && \ 424 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 425 !defined(CONFIG_M68K) 426 /* reserve memory for video display (always full pages) */ 427 gd->relocaddr = video_setmem(gd->relocaddr); 428 gd->fb_base = gd->relocaddr; 429 #endif 430 431 return 0; 432 } 433 434 static int reserve_trace(void) 435 { 436 #ifdef CONFIG_TRACE 437 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 438 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 439 debug("Reserving %dk for trace data at: %08lx\n", 440 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 441 #endif 442 443 return 0; 444 } 445 446 static int reserve_uboot(void) 447 { 448 if (!(gd->flags & GD_FLG_SKIP_RELOC)) { 449 /* 450 * reserve memory for U-Boot code, data & bss 451 * round down to next 4 kB limit 452 */ 453 gd->relocaddr -= gd->mon_len; 454 gd->relocaddr &= ~(4096 - 1); 455 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 456 /* round down to next 64 kB limit so that IVPR stays aligned */ 457 gd->relocaddr &= ~(65536 - 1); 458 #endif 459 460 debug("Reserving %ldk for U-Boot at: %08lx\n", 461 gd->mon_len >> 10, gd->relocaddr); 462 } 463 464 gd->start_addr_sp = gd->relocaddr; 465 466 return 0; 467 } 468 469 /* reserve memory for malloc() area */ 470 static int reserve_malloc(void) 471 { 472 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 473 debug("Reserving %dk for malloc() at: %08lx\n", 474 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 475 return 0; 476 } 477 478 /* (permanently) allocate a Board Info struct */ 479 static int reserve_board(void) 480 { 481 if (!gd->bd) { 482 gd->start_addr_sp -= sizeof(bd_t); 483 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 484 memset(gd->bd, '\0', sizeof(bd_t)); 485 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 486 sizeof(bd_t), gd->start_addr_sp); 487 } 488 return 0; 489 } 490 491 static int setup_machine(void) 492 { 493 #ifdef CONFIG_MACH_TYPE 494 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 495 #endif 496 return 0; 497 } 498 499 static int reserve_global_data(void) 500 { 501 gd->start_addr_sp -= sizeof(gd_t); 502 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 503 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 504 sizeof(gd_t), gd->start_addr_sp); 505 return 0; 506 } 507 508 static int reserve_fdt(void) 509 { 510 #ifndef CONFIG_OF_EMBED 511 /* 512 * If the device tree is sitting immediately above our image then we 513 * must relocate it. If it is embedded in the data section, then it 514 * will be relocated with other data. 515 */ 516 if (gd->fdt_blob) { 517 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 518 519 gd->start_addr_sp -= gd->fdt_size; 520 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 521 debug("Reserving %lu Bytes for FDT at: %08lx\n", 522 gd->fdt_size, gd->start_addr_sp); 523 } 524 #endif 525 526 return 0; 527 } 528 529 static int reserve_bootstage(void) 530 { 531 #ifdef CONFIG_BOOTSTAGE 532 int size = bootstage_get_size(); 533 534 gd->start_addr_sp -= size; 535 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 536 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 537 gd->start_addr_sp); 538 #endif 539 540 return 0; 541 } 542 543 __weak int arch_reserve_stacks(void) 544 { 545 return 0; 546 } 547 548 static int reserve_stacks(void) 549 { 550 /* make stack pointer 16-byte aligned */ 551 gd->start_addr_sp -= 16; 552 gd->start_addr_sp &= ~0xf; 553 554 /* 555 * let the architecture-specific code tailor gd->start_addr_sp and 556 * gd->irq_sp 557 */ 558 return arch_reserve_stacks(); 559 } 560 561 static int display_new_sp(void) 562 { 563 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 564 565 return 0; 566 } 567 568 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 569 defined(CONFIG_SH) 570 static int setup_board_part1(void) 571 { 572 bd_t *bd = gd->bd; 573 574 /* 575 * Save local variables to board info struct 576 */ 577 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 578 bd->bi_memsize = gd->ram_size; /* size in bytes */ 579 580 #ifdef CONFIG_SYS_SRAM_BASE 581 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 582 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 583 #endif 584 585 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 586 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 587 #endif 588 #if defined(CONFIG_M68K) 589 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 590 #endif 591 #if defined(CONFIG_MPC83xx) 592 bd->bi_immrbar = CONFIG_SYS_IMMR; 593 #endif 594 595 return 0; 596 } 597 #endif 598 599 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 600 static int setup_board_part2(void) 601 { 602 bd_t *bd = gd->bd; 603 604 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 605 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 606 #if defined(CONFIG_CPM2) 607 bd->bi_cpmfreq = gd->arch.cpm_clk; 608 bd->bi_brgfreq = gd->arch.brg_clk; 609 bd->bi_sccfreq = gd->arch.scc_clk; 610 bd->bi_vco = gd->arch.vco_out; 611 #endif /* CONFIG_CPM2 */ 612 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 613 bd->bi_pcifreq = gd->pci_clk; 614 #endif 615 #if defined(CONFIG_EXTRA_CLOCK) 616 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 617 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 618 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 619 #endif 620 621 return 0; 622 } 623 #endif 624 625 #ifdef CONFIG_POST 626 static int init_post(void) 627 { 628 post_bootmode_init(); 629 post_run(NULL, POST_ROM | post_bootmode_get(0)); 630 631 return 0; 632 } 633 #endif 634 635 static int reloc_fdt(void) 636 { 637 #ifndef CONFIG_OF_EMBED 638 if (gd->flags & GD_FLG_SKIP_RELOC) 639 return 0; 640 if (gd->new_fdt) { 641 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 642 gd->fdt_blob = gd->new_fdt; 643 } 644 #endif 645 646 return 0; 647 } 648 649 static int reloc_bootstage(void) 650 { 651 #ifdef CONFIG_BOOTSTAGE 652 if (gd->flags & GD_FLG_SKIP_RELOC) 653 return 0; 654 if (gd->new_bootstage) { 655 int size = bootstage_get_size(); 656 657 debug("Copying bootstage from %p to %p, size %x\n", 658 gd->bootstage, gd->new_bootstage, size); 659 memcpy(gd->new_bootstage, gd->bootstage, size); 660 gd->bootstage = gd->new_bootstage; 661 } 662 #endif 663 664 return 0; 665 } 666 667 static int setup_reloc(void) 668 { 669 if (gd->flags & GD_FLG_SKIP_RELOC) { 670 debug("Skipping relocation due to flag\n"); 671 return 0; 672 } 673 674 #ifdef CONFIG_SYS_TEXT_BASE 675 #ifdef ARM 676 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 677 #elif defined(CONFIG_M68K) 678 /* 679 * On all ColdFire arch cpu, monitor code starts always 680 * just after the default vector table location, so at 0x400 681 */ 682 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 683 #else 684 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 685 #endif 686 #endif 687 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 688 689 debug("Relocation Offset is: %08lx\n", gd->reloc_off); 690 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 691 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 692 gd->start_addr_sp); 693 694 return 0; 695 } 696 697 #ifdef CONFIG_OF_BOARD_FIXUP 698 static int fix_fdt(void) 699 { 700 return board_fix_fdt((void *)gd->fdt_blob); 701 } 702 #endif 703 704 /* ARM calls relocate_code from its crt0.S */ 705 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 706 !CONFIG_IS_ENABLED(X86_64) 707 708 static int jump_to_copy(void) 709 { 710 if (gd->flags & GD_FLG_SKIP_RELOC) 711 return 0; 712 /* 713 * x86 is special, but in a nice way. It uses a trampoline which 714 * enables the dcache if possible. 715 * 716 * For now, other archs use relocate_code(), which is implemented 717 * similarly for all archs. When we do generic relocation, hopefully 718 * we can make all archs enable the dcache prior to relocation. 719 */ 720 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 721 /* 722 * SDRAM and console are now initialised. The final stack can now 723 * be setup in SDRAM. Code execution will continue in Flash, but 724 * with the stack in SDRAM and Global Data in temporary memory 725 * (CPU cache) 726 */ 727 arch_setup_gd(gd->new_gd); 728 board_init_f_r_trampoline(gd->start_addr_sp); 729 #else 730 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 731 #endif 732 733 return 0; 734 } 735 #endif 736 737 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 738 static int initf_bootstage(void) 739 { 740 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 741 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 742 int ret; 743 744 ret = bootstage_init(!from_spl); 745 if (ret) 746 return ret; 747 if (from_spl) { 748 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 749 CONFIG_BOOTSTAGE_STASH_SIZE); 750 751 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 752 if (ret && ret != -ENOENT) { 753 debug("Failed to unstash bootstage: err=%d\n", ret); 754 return ret; 755 } 756 } 757 758 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 759 760 return 0; 761 } 762 763 static int initf_console_record(void) 764 { 765 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 766 return console_record_init(); 767 #else 768 return 0; 769 #endif 770 } 771 772 static int initf_dm(void) 773 { 774 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 775 int ret; 776 777 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 778 ret = dm_init_and_scan(true); 779 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 780 if (ret) 781 return ret; 782 #endif 783 #ifdef CONFIG_TIMER_EARLY 784 ret = dm_timer_init(); 785 if (ret) 786 return ret; 787 #endif 788 789 return 0; 790 } 791 792 /* Architecture-specific memory reservation */ 793 __weak int reserve_arch(void) 794 { 795 return 0; 796 } 797 798 __weak int arch_cpu_init_dm(void) 799 { 800 return 0; 801 } 802 803 static const init_fnc_t init_sequence_f[] = { 804 setup_mon_len, 805 #ifdef CONFIG_OF_CONTROL 806 fdtdec_setup, 807 #endif 808 #ifdef CONFIG_TRACE 809 trace_early_init, 810 #endif 811 initf_malloc, 812 log_init, 813 initf_bootstage, /* uses its own timer, so does not need DM */ 814 initf_console_record, 815 #if defined(CONFIG_HAVE_FSP) 816 arch_fsp_init, 817 #endif 818 arch_cpu_init, /* basic arch cpu dependent setup */ 819 mach_cpu_init, /* SoC/machine dependent CPU setup */ 820 initf_dm, 821 arch_cpu_init_dm, 822 #if defined(CONFIG_BOARD_EARLY_INIT_F) 823 board_early_init_f, 824 #endif 825 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 826 /* get CPU and bus clocks according to the environment variable */ 827 get_clocks, /* get CPU and bus clocks (etc.) */ 828 #endif 829 #if !defined(CONFIG_M68K) 830 timer_init, /* initialize timer */ 831 #endif 832 #if defined(CONFIG_BOARD_POSTCLK_INIT) 833 board_postclk_init, 834 #endif 835 env_init, /* initialize environment */ 836 init_baud_rate, /* initialze baudrate settings */ 837 serial_init, /* serial communications setup */ 838 console_init_f, /* stage 1 init of console */ 839 display_options, /* say that we are here */ 840 display_text_info, /* show debugging info if required */ 841 #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86) 842 checkcpu, 843 #endif 844 #if defined(CONFIG_SYSRESET) 845 print_resetinfo, 846 #endif 847 #if defined(CONFIG_DISPLAY_CPUINFO) 848 print_cpuinfo, /* display cpu info (and speed) */ 849 #endif 850 #if defined(CONFIG_DTB_RESELECT) 851 embedded_dtb_select, 852 #endif 853 #if defined(CONFIG_DISPLAY_BOARDINFO) 854 show_board_info, 855 #endif 856 INIT_FUNC_WATCHDOG_INIT 857 #if defined(CONFIG_MISC_INIT_F) 858 misc_init_f, 859 #endif 860 INIT_FUNC_WATCHDOG_RESET 861 #if defined(CONFIG_SYS_I2C) 862 init_func_i2c, 863 #endif 864 #if defined(CONFIG_VID) && !defined(CONFIG_SPL) 865 init_func_vid, 866 #endif 867 #if defined(CONFIG_HARD_SPI) 868 init_func_spi, 869 #endif 870 announce_dram_init, 871 dram_init, /* configure available RAM banks */ 872 #ifdef CONFIG_POST 873 post_init_f, 874 #endif 875 INIT_FUNC_WATCHDOG_RESET 876 #if defined(CONFIG_SYS_DRAM_TEST) 877 testdram, 878 #endif /* CONFIG_SYS_DRAM_TEST */ 879 INIT_FUNC_WATCHDOG_RESET 880 881 #ifdef CONFIG_POST 882 init_post, 883 #endif 884 INIT_FUNC_WATCHDOG_RESET 885 /* 886 * Now that we have DRAM mapped and working, we can 887 * relocate the code and continue running from DRAM. 888 * 889 * Reserve memory at end of RAM for (top down in that order): 890 * - area that won't get touched by U-Boot and Linux (optional) 891 * - kernel log buffer 892 * - protected RAM 893 * - LCD framebuffer 894 * - monitor code 895 * - board info struct 896 */ 897 setup_dest_addr, 898 #ifdef CONFIG_PRAM 899 reserve_pram, 900 #endif 901 reserve_round_4k, 902 #ifdef CONFIG_ARM 903 reserve_mmu, 904 #endif 905 reserve_video, 906 reserve_trace, 907 reserve_uboot, 908 reserve_malloc, 909 reserve_board, 910 setup_machine, 911 reserve_global_data, 912 reserve_fdt, 913 reserve_bootstage, 914 reserve_arch, 915 reserve_stacks, 916 dram_init_banksize, 917 show_dram_config, 918 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 919 defined(CONFIG_SH) 920 setup_board_part1, 921 #endif 922 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 923 INIT_FUNC_WATCHDOG_RESET 924 setup_board_part2, 925 #endif 926 display_new_sp, 927 #ifdef CONFIG_OF_BOARD_FIXUP 928 fix_fdt, 929 #endif 930 INIT_FUNC_WATCHDOG_RESET 931 reloc_fdt, 932 reloc_bootstage, 933 setup_reloc, 934 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 935 copy_uboot_to_ram, 936 do_elf_reloc_fixups, 937 clear_bss, 938 #endif 939 #if defined(CONFIG_XTENSA) 940 clear_bss, 941 #endif 942 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 943 !CONFIG_IS_ENABLED(X86_64) 944 jump_to_copy, 945 #endif 946 NULL, 947 }; 948 949 void board_init_f(ulong boot_flags) 950 { 951 gd->flags = boot_flags; 952 gd->have_console = 0; 953 954 if (initcall_run_list(init_sequence_f)) 955 hang(); 956 957 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 958 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \ 959 !defined(CONFIG_ARC) 960 /* NOTREACHED - jump_to_copy() does not return */ 961 hang(); 962 #endif 963 } 964 965 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 966 /* 967 * For now this code is only used on x86. 968 * 969 * init_sequence_f_r is the list of init functions which are run when 970 * U-Boot is executing from Flash with a semi-limited 'C' environment. 971 * The following limitations must be considered when implementing an 972 * '_f_r' function: 973 * - 'static' variables are read-only 974 * - Global Data (gd->xxx) is read/write 975 * 976 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 977 * supported). It _should_, if possible, copy global data to RAM and 978 * initialise the CPU caches (to speed up the relocation process) 979 * 980 * NOTE: At present only x86 uses this route, but it is intended that 981 * all archs will move to this when generic relocation is implemented. 982 */ 983 static const init_fnc_t init_sequence_f_r[] = { 984 #if !CONFIG_IS_ENABLED(X86_64) 985 init_cache_f_r, 986 #endif 987 988 NULL, 989 }; 990 991 void board_init_f_r(void) 992 { 993 if (initcall_run_list(init_sequence_f_r)) 994 hang(); 995 996 /* 997 * The pre-relocation drivers may be using memory that has now gone 998 * away. Mark serial as unavailable - this will fall back to the debug 999 * UART if available. 1000 * 1001 * Do the same with log drivers since the memory may not be available. 1002 */ 1003 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); 1004 #ifdef CONFIG_TIMER 1005 gd->timer = NULL; 1006 #endif 1007 1008 /* 1009 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 1010 * Transfer execution from Flash to RAM by calculating the address 1011 * of the in-RAM copy of board_init_r() and calling it 1012 */ 1013 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 1014 1015 /* NOTREACHED - board_init_r() does not return */ 1016 hang(); 1017 } 1018 #endif /* CONFIG_X86 */ 1019