1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * (C) Copyright 2002-2006 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * (C) Copyright 2002 8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 9 * Marius Groeger <mgroeger@sysgo.de> 10 */ 11 12 #include <common.h> 13 #include <console.h> 14 #include <environment.h> 15 #include <dm.h> 16 #include <fdtdec.h> 17 #include <fs.h> 18 #include <i2c.h> 19 #include <initcall.h> 20 #include <malloc.h> 21 #include <mapmem.h> 22 #include <os.h> 23 #include <post.h> 24 #include <relocate.h> 25 #include <spi.h> 26 #include <status_led.h> 27 #include <timer.h> 28 #include <trace.h> 29 #include <video.h> 30 #include <watchdog.h> 31 #ifdef CONFIG_MACH_TYPE 32 #include <asm/mach-types.h> 33 #endif 34 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 35 #include <asm/mp.h> 36 #endif 37 #include <asm/io.h> 38 #include <asm/sections.h> 39 #include <dm/root.h> 40 #include <linux/errno.h> 41 42 /* 43 * Pointer to initial global data area 44 * 45 * Here we initialize it if needed. 46 */ 47 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 48 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 49 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 50 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR); 51 #else 52 DECLARE_GLOBAL_DATA_PTR; 53 #endif 54 55 /* 56 * TODO(sjg@chromium.org): IMO this code should be 57 * refactored to a single function, something like: 58 * 59 * void led_set_state(enum led_colour_t colour, int on); 60 */ 61 /************************************************************************ 62 * Coloured LED functionality 63 ************************************************************************ 64 * May be supplied by boards if desired 65 */ 66 __weak void coloured_LED_init(void) {} 67 __weak void red_led_on(void) {} 68 __weak void red_led_off(void) {} 69 __weak void green_led_on(void) {} 70 __weak void green_led_off(void) {} 71 __weak void yellow_led_on(void) {} 72 __weak void yellow_led_off(void) {} 73 __weak void blue_led_on(void) {} 74 __weak void blue_led_off(void) {} 75 76 /* 77 * Why is gd allocated a register? Prior to reloc it might be better to 78 * just pass it around to each function in this file? 79 * 80 * After reloc one could argue that it is hardly used and doesn't need 81 * to be in a register. Or if it is it should perhaps hold pointers to all 82 * global data for all modules, so that post-reloc we can avoid the massive 83 * literal pool we get on ARM. Or perhaps just encourage each module to use 84 * a structure... 85 */ 86 87 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 88 static int init_func_watchdog_init(void) 89 { 90 # if defined(CONFIG_HW_WATCHDOG) && \ 91 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 92 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ 93 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 94 defined(CONFIG_IMX_WATCHDOG)) 95 hw_watchdog_init(); 96 puts(" Watchdog enabled\n"); 97 # endif 98 WATCHDOG_RESET(); 99 100 return 0; 101 } 102 103 int init_func_watchdog_reset(void) 104 { 105 WATCHDOG_RESET(); 106 107 return 0; 108 } 109 #endif /* CONFIG_WATCHDOG */ 110 111 __weak void board_add_ram_info(int use_default) 112 { 113 /* please define platform specific board_add_ram_info() */ 114 } 115 116 static int init_baud_rate(void) 117 { 118 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 119 return 0; 120 } 121 122 static int display_text_info(void) 123 { 124 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 125 ulong bss_start, bss_end, text_base; 126 127 bss_start = (ulong)&__bss_start; 128 bss_end = (ulong)&__bss_end; 129 130 #ifdef CONFIG_SYS_TEXT_BASE 131 text_base = CONFIG_SYS_TEXT_BASE; 132 #else 133 text_base = CONFIG_SYS_MONITOR_BASE; 134 #endif 135 136 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 137 text_base, bss_start, bss_end); 138 #endif 139 140 return 0; 141 } 142 143 static int announce_dram_init(void) 144 { 145 puts("DRAM: "); 146 return 0; 147 } 148 149 static int show_dram_config(void) 150 { 151 unsigned long long size; 152 153 #ifdef CONFIG_NR_DRAM_BANKS 154 int i; 155 156 debug("\nRAM Configuration:\n"); 157 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 158 size += gd->bd->bi_dram[i].size; 159 debug("Bank #%d: %llx ", i, 160 (unsigned long long)(gd->bd->bi_dram[i].start)); 161 #ifdef DEBUG 162 print_size(gd->bd->bi_dram[i].size, "\n"); 163 #endif 164 } 165 debug("\nDRAM: "); 166 #else 167 size = gd->ram_size; 168 #endif 169 170 print_size(size, ""); 171 board_add_ram_info(0); 172 putc('\n'); 173 174 return 0; 175 } 176 177 __weak int dram_init_banksize(void) 178 { 179 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 180 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 181 gd->bd->bi_dram[0].size = get_effective_memsize(); 182 #endif 183 184 return 0; 185 } 186 187 #if defined(CONFIG_SYS_I2C) 188 static int init_func_i2c(void) 189 { 190 puts("I2C: "); 191 #ifdef CONFIG_SYS_I2C 192 i2c_init_all(); 193 #else 194 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 195 #endif 196 puts("ready\n"); 197 return 0; 198 } 199 #endif 200 201 #if defined(CONFIG_VID) 202 __weak int init_func_vid(void) 203 { 204 return 0; 205 } 206 #endif 207 208 #if defined(CONFIG_HARD_SPI) 209 static int init_func_spi(void) 210 { 211 puts("SPI: "); 212 spi_init(); 213 puts("ready\n"); 214 return 0; 215 } 216 #endif 217 218 static int setup_mon_len(void) 219 { 220 #if defined(__ARM__) || defined(__MICROBLAZE__) 221 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 222 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 223 gd->mon_len = (ulong)&_end - (ulong)_init; 224 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 225 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 226 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV) 227 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 228 #elif defined(CONFIG_SYS_MONITOR_BASE) 229 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 230 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 231 #endif 232 return 0; 233 } 234 235 __weak int arch_cpu_init(void) 236 { 237 return 0; 238 } 239 240 __weak int mach_cpu_init(void) 241 { 242 return 0; 243 } 244 245 /* Get the top of usable RAM */ 246 __weak ulong board_get_usable_ram_top(ulong total_size) 247 { 248 #ifdef CONFIG_SYS_SDRAM_BASE 249 /* 250 * Detect whether we have so much RAM that it goes past the end of our 251 * 32-bit address space. If so, clip the usable RAM so it doesn't. 252 */ 253 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 254 /* 255 * Will wrap back to top of 32-bit space when reservations 256 * are made. 257 */ 258 return 0; 259 #endif 260 return gd->ram_top; 261 } 262 263 static int setup_dest_addr(void) 264 { 265 debug("Monitor len: %08lX\n", gd->mon_len); 266 /* 267 * Ram is setup, size stored in gd !! 268 */ 269 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 270 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 271 /* 272 * Subtract specified amount of memory to hide so that it won't 273 * get "touched" at all by U-Boot. By fixing up gd->ram_size 274 * the Linux kernel should now get passed the now "corrected" 275 * memory size and won't touch it either. This should work 276 * for arch/ppc and arch/powerpc. Only Linux board ports in 277 * arch/powerpc with bootwrapper support, that recalculate the 278 * memory size from the SDRAM controller setup will have to 279 * get fixed. 280 */ 281 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 282 #endif 283 #ifdef CONFIG_SYS_SDRAM_BASE 284 gd->ram_top = CONFIG_SYS_SDRAM_BASE; 285 #endif 286 gd->ram_top += get_effective_memsize(); 287 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 288 gd->relocaddr = gd->ram_top; 289 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 290 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 291 /* 292 * We need to make sure the location we intend to put secondary core 293 * boot code is reserved and not used by any part of u-boot 294 */ 295 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 296 gd->relocaddr = determine_mp_bootpg(NULL); 297 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 298 } 299 #endif 300 return 0; 301 } 302 303 #ifdef CONFIG_PRAM 304 /* reserve protected RAM */ 305 static int reserve_pram(void) 306 { 307 ulong reg; 308 309 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 310 gd->relocaddr -= (reg << 10); /* size is in kB */ 311 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 312 gd->relocaddr); 313 return 0; 314 } 315 #endif /* CONFIG_PRAM */ 316 317 /* Round memory pointer down to next 4 kB limit */ 318 static int reserve_round_4k(void) 319 { 320 gd->relocaddr &= ~(4096 - 1); 321 return 0; 322 } 323 324 #ifdef CONFIG_ARM 325 __weak int reserve_mmu(void) 326 { 327 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 328 /* reserve TLB table */ 329 gd->arch.tlb_size = PGTABLE_SIZE; 330 gd->relocaddr -= gd->arch.tlb_size; 331 332 /* round down to next 64 kB limit */ 333 gd->relocaddr &= ~(0x10000 - 1); 334 335 gd->arch.tlb_addr = gd->relocaddr; 336 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 337 gd->arch.tlb_addr + gd->arch.tlb_size); 338 339 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 340 /* 341 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 342 * with location within secure ram. 343 */ 344 gd->arch.tlb_allocated = gd->arch.tlb_addr; 345 #endif 346 #endif 347 348 return 0; 349 } 350 #endif 351 352 static int reserve_video(void) 353 { 354 #ifdef CONFIG_DM_VIDEO 355 ulong addr; 356 int ret; 357 358 addr = gd->relocaddr; 359 ret = video_reserve(&addr); 360 if (ret) 361 return ret; 362 gd->relocaddr = addr; 363 #elif defined(CONFIG_LCD) 364 # ifdef CONFIG_FB_ADDR 365 gd->fb_base = CONFIG_FB_ADDR; 366 # else 367 /* reserve memory for LCD display (always full pages) */ 368 gd->relocaddr = lcd_setmem(gd->relocaddr); 369 gd->fb_base = gd->relocaddr; 370 # endif /* CONFIG_FB_ADDR */ 371 #elif defined(CONFIG_VIDEO) && \ 372 (!defined(CONFIG_PPC)) && \ 373 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 374 !defined(CONFIG_M68K) 375 /* reserve memory for video display (always full pages) */ 376 gd->relocaddr = video_setmem(gd->relocaddr); 377 gd->fb_base = gd->relocaddr; 378 #endif 379 380 return 0; 381 } 382 383 static int reserve_trace(void) 384 { 385 #ifdef CONFIG_TRACE 386 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 387 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 388 debug("Reserving %dk for trace data at: %08lx\n", 389 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 390 #endif 391 392 return 0; 393 } 394 395 static int reserve_uboot(void) 396 { 397 /* 398 * reserve memory for U-Boot code, data & bss 399 * round down to next 4 kB limit 400 */ 401 gd->relocaddr -= gd->mon_len; 402 gd->relocaddr &= ~(4096 - 1); 403 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 404 /* round down to next 64 kB limit so that IVPR stays aligned */ 405 gd->relocaddr &= ~(65536 - 1); 406 #endif 407 408 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, 409 gd->relocaddr); 410 411 gd->start_addr_sp = gd->relocaddr; 412 413 return 0; 414 } 415 416 /* reserve memory for malloc() area */ 417 static int reserve_malloc(void) 418 { 419 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 420 debug("Reserving %dk for malloc() at: %08lx\n", 421 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 422 return 0; 423 } 424 425 /* (permanently) allocate a Board Info struct */ 426 static int reserve_board(void) 427 { 428 if (!gd->bd) { 429 gd->start_addr_sp -= sizeof(bd_t); 430 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 431 memset(gd->bd, '\0', sizeof(bd_t)); 432 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 433 sizeof(bd_t), gd->start_addr_sp); 434 } 435 return 0; 436 } 437 438 static int setup_machine(void) 439 { 440 #ifdef CONFIG_MACH_TYPE 441 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 442 #endif 443 return 0; 444 } 445 446 static int reserve_global_data(void) 447 { 448 gd->start_addr_sp -= sizeof(gd_t); 449 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 450 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 451 sizeof(gd_t), gd->start_addr_sp); 452 return 0; 453 } 454 455 static int reserve_fdt(void) 456 { 457 #ifndef CONFIG_OF_EMBED 458 /* 459 * If the device tree is sitting immediately above our image then we 460 * must relocate it. If it is embedded in the data section, then it 461 * will be relocated with other data. 462 */ 463 if (gd->fdt_blob) { 464 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 465 466 gd->start_addr_sp -= gd->fdt_size; 467 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 468 debug("Reserving %lu Bytes for FDT at: %08lx\n", 469 gd->fdt_size, gd->start_addr_sp); 470 } 471 #endif 472 473 return 0; 474 } 475 476 static int reserve_bootstage(void) 477 { 478 #ifdef CONFIG_BOOTSTAGE 479 int size = bootstage_get_size(); 480 481 gd->start_addr_sp -= size; 482 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 483 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 484 gd->start_addr_sp); 485 #endif 486 487 return 0; 488 } 489 490 __weak int arch_reserve_stacks(void) 491 { 492 return 0; 493 } 494 495 static int reserve_stacks(void) 496 { 497 /* make stack pointer 16-byte aligned */ 498 gd->start_addr_sp -= 16; 499 gd->start_addr_sp &= ~0xf; 500 501 /* 502 * let the architecture-specific code tailor gd->start_addr_sp and 503 * gd->irq_sp 504 */ 505 return arch_reserve_stacks(); 506 } 507 508 static int display_new_sp(void) 509 { 510 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 511 512 return 0; 513 } 514 515 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 516 defined(CONFIG_SH) 517 static int setup_board_part1(void) 518 { 519 bd_t *bd = gd->bd; 520 521 /* 522 * Save local variables to board info struct 523 */ 524 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 525 bd->bi_memsize = gd->ram_size; /* size in bytes */ 526 527 #ifdef CONFIG_SYS_SRAM_BASE 528 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 529 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 530 #endif 531 532 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 533 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 534 #endif 535 #if defined(CONFIG_M68K) 536 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 537 #endif 538 #if defined(CONFIG_MPC83xx) 539 bd->bi_immrbar = CONFIG_SYS_IMMR; 540 #endif 541 542 return 0; 543 } 544 #endif 545 546 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 547 static int setup_board_part2(void) 548 { 549 bd_t *bd = gd->bd; 550 551 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 552 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 553 #if defined(CONFIG_CPM2) 554 bd->bi_cpmfreq = gd->arch.cpm_clk; 555 bd->bi_brgfreq = gd->arch.brg_clk; 556 bd->bi_sccfreq = gd->arch.scc_clk; 557 bd->bi_vco = gd->arch.vco_out; 558 #endif /* CONFIG_CPM2 */ 559 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 560 bd->bi_pcifreq = gd->pci_clk; 561 #endif 562 #if defined(CONFIG_EXTRA_CLOCK) 563 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 564 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 565 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 566 #endif 567 568 return 0; 569 } 570 #endif 571 572 #ifdef CONFIG_POST 573 static int init_post(void) 574 { 575 post_bootmode_init(); 576 post_run(NULL, POST_ROM | post_bootmode_get(0)); 577 578 return 0; 579 } 580 #endif 581 582 static int reloc_fdt(void) 583 { 584 #ifndef CONFIG_OF_EMBED 585 if (gd->flags & GD_FLG_SKIP_RELOC) 586 return 0; 587 if (gd->new_fdt) { 588 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 589 gd->fdt_blob = gd->new_fdt; 590 } 591 #endif 592 593 return 0; 594 } 595 596 static int reloc_bootstage(void) 597 { 598 #ifdef CONFIG_BOOTSTAGE 599 if (gd->flags & GD_FLG_SKIP_RELOC) 600 return 0; 601 if (gd->new_bootstage) { 602 int size = bootstage_get_size(); 603 604 debug("Copying bootstage from %p to %p, size %x\n", 605 gd->bootstage, gd->new_bootstage, size); 606 memcpy(gd->new_bootstage, gd->bootstage, size); 607 gd->bootstage = gd->new_bootstage; 608 } 609 #endif 610 611 return 0; 612 } 613 614 static int setup_reloc(void) 615 { 616 if (gd->flags & GD_FLG_SKIP_RELOC) { 617 debug("Skipping relocation due to flag\n"); 618 return 0; 619 } 620 621 #ifdef CONFIG_SYS_TEXT_BASE 622 #ifdef ARM 623 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 624 #elif defined(CONFIG_M68K) 625 /* 626 * On all ColdFire arch cpu, monitor code starts always 627 * just after the default vector table location, so at 0x400 628 */ 629 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 630 #else 631 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 632 #endif 633 #endif 634 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 635 636 debug("Relocation Offset is: %08lx\n", gd->reloc_off); 637 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 638 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 639 gd->start_addr_sp); 640 641 return 0; 642 } 643 644 #ifdef CONFIG_OF_BOARD_FIXUP 645 static int fix_fdt(void) 646 { 647 return board_fix_fdt((void *)gd->fdt_blob); 648 } 649 #endif 650 651 /* ARM calls relocate_code from its crt0.S */ 652 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 653 !CONFIG_IS_ENABLED(X86_64) 654 655 static int jump_to_copy(void) 656 { 657 if (gd->flags & GD_FLG_SKIP_RELOC) 658 return 0; 659 /* 660 * x86 is special, but in a nice way. It uses a trampoline which 661 * enables the dcache if possible. 662 * 663 * For now, other archs use relocate_code(), which is implemented 664 * similarly for all archs. When we do generic relocation, hopefully 665 * we can make all archs enable the dcache prior to relocation. 666 */ 667 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 668 /* 669 * SDRAM and console are now initialised. The final stack can now 670 * be setup in SDRAM. Code execution will continue in Flash, but 671 * with the stack in SDRAM and Global Data in temporary memory 672 * (CPU cache) 673 */ 674 arch_setup_gd(gd->new_gd); 675 board_init_f_r_trampoline(gd->start_addr_sp); 676 #else 677 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 678 #endif 679 680 return 0; 681 } 682 #endif 683 684 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 685 static int initf_bootstage(void) 686 { 687 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 688 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 689 int ret; 690 691 ret = bootstage_init(!from_spl); 692 if (ret) 693 return ret; 694 if (from_spl) { 695 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 696 CONFIG_BOOTSTAGE_STASH_SIZE); 697 698 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 699 if (ret && ret != -ENOENT) { 700 debug("Failed to unstash bootstage: err=%d\n", ret); 701 return ret; 702 } 703 } 704 705 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 706 707 return 0; 708 } 709 710 static int initf_console_record(void) 711 { 712 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 713 return console_record_init(); 714 #else 715 return 0; 716 #endif 717 } 718 719 static int initf_dm(void) 720 { 721 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 722 int ret; 723 724 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 725 ret = dm_init_and_scan(true); 726 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 727 if (ret) 728 return ret; 729 #endif 730 #ifdef CONFIG_TIMER_EARLY 731 ret = dm_timer_init(); 732 if (ret) 733 return ret; 734 #endif 735 736 return 0; 737 } 738 739 /* Architecture-specific memory reservation */ 740 __weak int reserve_arch(void) 741 { 742 return 0; 743 } 744 745 __weak int arch_cpu_init_dm(void) 746 { 747 return 0; 748 } 749 750 static const init_fnc_t init_sequence_f[] = { 751 setup_mon_len, 752 #ifdef CONFIG_OF_CONTROL 753 fdtdec_setup, 754 #endif 755 #ifdef CONFIG_TRACE 756 trace_early_init, 757 #endif 758 initf_malloc, 759 log_init, 760 initf_bootstage, /* uses its own timer, so does not need DM */ 761 initf_console_record, 762 #if defined(CONFIG_HAVE_FSP) 763 arch_fsp_init, 764 #endif 765 arch_cpu_init, /* basic arch cpu dependent setup */ 766 mach_cpu_init, /* SoC/machine dependent CPU setup */ 767 initf_dm, 768 arch_cpu_init_dm, 769 #if defined(CONFIG_BOARD_EARLY_INIT_F) 770 board_early_init_f, 771 #endif 772 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 773 /* get CPU and bus clocks according to the environment variable */ 774 get_clocks, /* get CPU and bus clocks (etc.) */ 775 #endif 776 #if !defined(CONFIG_M68K) 777 timer_init, /* initialize timer */ 778 #endif 779 #if defined(CONFIG_BOARD_POSTCLK_INIT) 780 board_postclk_init, 781 #endif 782 env_init, /* initialize environment */ 783 init_baud_rate, /* initialze baudrate settings */ 784 serial_init, /* serial communications setup */ 785 console_init_f, /* stage 1 init of console */ 786 display_options, /* say that we are here */ 787 display_text_info, /* show debugging info if required */ 788 #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86) 789 checkcpu, 790 #endif 791 #if defined(CONFIG_DISPLAY_CPUINFO) 792 print_cpuinfo, /* display cpu info (and speed) */ 793 #endif 794 #if defined(CONFIG_DTB_RESELECT) 795 embedded_dtb_select, 796 #endif 797 #if defined(CONFIG_DISPLAY_BOARDINFO) 798 show_board_info, 799 #endif 800 INIT_FUNC_WATCHDOG_INIT 801 #if defined(CONFIG_MISC_INIT_F) 802 misc_init_f, 803 #endif 804 INIT_FUNC_WATCHDOG_RESET 805 #if defined(CONFIG_SYS_I2C) 806 init_func_i2c, 807 #endif 808 #if defined(CONFIG_VID) && !defined(CONFIG_SPL) 809 init_func_vid, 810 #endif 811 #if defined(CONFIG_HARD_SPI) 812 init_func_spi, 813 #endif 814 announce_dram_init, 815 dram_init, /* configure available RAM banks */ 816 #ifdef CONFIG_POST 817 post_init_f, 818 #endif 819 INIT_FUNC_WATCHDOG_RESET 820 #if defined(CONFIG_SYS_DRAM_TEST) 821 testdram, 822 #endif /* CONFIG_SYS_DRAM_TEST */ 823 INIT_FUNC_WATCHDOG_RESET 824 825 #ifdef CONFIG_POST 826 init_post, 827 #endif 828 INIT_FUNC_WATCHDOG_RESET 829 /* 830 * Now that we have DRAM mapped and working, we can 831 * relocate the code and continue running from DRAM. 832 * 833 * Reserve memory at end of RAM for (top down in that order): 834 * - area that won't get touched by U-Boot and Linux (optional) 835 * - kernel log buffer 836 * - protected RAM 837 * - LCD framebuffer 838 * - monitor code 839 * - board info struct 840 */ 841 setup_dest_addr, 842 #ifdef CONFIG_PRAM 843 reserve_pram, 844 #endif 845 reserve_round_4k, 846 #ifdef CONFIG_ARM 847 reserve_mmu, 848 #endif 849 reserve_video, 850 reserve_trace, 851 reserve_uboot, 852 reserve_malloc, 853 reserve_board, 854 setup_machine, 855 reserve_global_data, 856 reserve_fdt, 857 reserve_bootstage, 858 reserve_arch, 859 reserve_stacks, 860 dram_init_banksize, 861 show_dram_config, 862 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 863 defined(CONFIG_SH) 864 setup_board_part1, 865 #endif 866 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 867 INIT_FUNC_WATCHDOG_RESET 868 setup_board_part2, 869 #endif 870 display_new_sp, 871 #ifdef CONFIG_OF_BOARD_FIXUP 872 fix_fdt, 873 #endif 874 INIT_FUNC_WATCHDOG_RESET 875 reloc_fdt, 876 reloc_bootstage, 877 setup_reloc, 878 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 879 copy_uboot_to_ram, 880 do_elf_reloc_fixups, 881 clear_bss, 882 #endif 883 #if defined(CONFIG_XTENSA) 884 clear_bss, 885 #endif 886 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 887 !CONFIG_IS_ENABLED(X86_64) 888 jump_to_copy, 889 #endif 890 NULL, 891 }; 892 893 void board_init_f(ulong boot_flags) 894 { 895 gd->flags = boot_flags; 896 gd->have_console = 0; 897 898 if (initcall_run_list(init_sequence_f)) 899 hang(); 900 901 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 902 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \ 903 !defined(CONFIG_ARC) 904 /* NOTREACHED - jump_to_copy() does not return */ 905 hang(); 906 #endif 907 } 908 909 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 910 /* 911 * For now this code is only used on x86. 912 * 913 * init_sequence_f_r is the list of init functions which are run when 914 * U-Boot is executing from Flash with a semi-limited 'C' environment. 915 * The following limitations must be considered when implementing an 916 * '_f_r' function: 917 * - 'static' variables are read-only 918 * - Global Data (gd->xxx) is read/write 919 * 920 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 921 * supported). It _should_, if possible, copy global data to RAM and 922 * initialise the CPU caches (to speed up the relocation process) 923 * 924 * NOTE: At present only x86 uses this route, but it is intended that 925 * all archs will move to this when generic relocation is implemented. 926 */ 927 static const init_fnc_t init_sequence_f_r[] = { 928 #if !CONFIG_IS_ENABLED(X86_64) 929 init_cache_f_r, 930 #endif 931 932 NULL, 933 }; 934 935 void board_init_f_r(void) 936 { 937 if (initcall_run_list(init_sequence_f_r)) 938 hang(); 939 940 /* 941 * The pre-relocation drivers may be using memory that has now gone 942 * away. Mark serial as unavailable - this will fall back to the debug 943 * UART if available. 944 * 945 * Do the same with log drivers since the memory may not be available. 946 */ 947 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); 948 #ifdef CONFIG_TIMER 949 gd->timer = NULL; 950 #endif 951 952 /* 953 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 954 * Transfer execution from Flash to RAM by calculating the address 955 * of the in-RAM copy of board_init_r() and calling it 956 */ 957 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 958 959 /* NOTREACHED - board_init_r() does not return */ 960 hang(); 961 } 962 #endif /* CONFIG_X86 */ 963